replacing all ifndef with pargma once

All the kernel header files now use pargma once rather than the ifndef,
as the pre-processed C files do not change while header files
are protected with pargma once. This will also solve any naming issues
caused by ifndef.

Convert license tags to SPDX identifiers

This commit also converts our own copyright headers to directly use
SPDX, but leaves all other copyright header intact, only adding the
SPDX ident. As far as possible this commit also merges multiple
Data61 copyright statements/headers into one for consistency.

mcs: tickless driver for x86

Add a tickless timer driver for x86. The driver defaults to using
TSC_DEADLINE mode, but falls back to the apic if that feature is not
available.

Add syscall for setting the current TLS register.

Some platforms and configurations do not allow user code to change the
value of the register used for TLS. On these architectures a syscall can
be used to allow the kernel to update the register on their behalf.

This does not immediately update the value in the user context on many
configurations as the values are only stored in the user context on a
context switch.

RFC-3: Update context for x86 to use FS and GS.

TLS_BASE virtual register is replaced with FS_BASE and GS_BASE virtual
registers.

The FS_BASE and GS_BASE virtual registers are moved to the end of the
context so they need not be considered in the kernel exit and entry
implementation.

Removed tracking of ES, DS, FS, and GS segment selectors on kernel entry
and exit.

ES and DS are clobbered on kernel entry with the RPL 3 selector for a
DPL 3 linear data segment.

FS is clobbered on exit with the RPL 3 selector for the DPL 3 segment
with FS_BASE as the base. This is done on exit to reload the value from
the GDT.

GS is clobbered on exit with the RPL 3 selector for the DPL 3 segment
with GS_BASE as the base. This is done on exit to reload the value from
the GDT.

Kernel entry and exit code is refactored, simplified, and improved in
light of the above changes.

x64: update verified config to use fsgsbase instr

The verification platform for x64 relies on the fsgsbase instruction.

style: consistently align pointer with name

Run astyle with align-pointer=name

style: correct parenthesis padding

Use astyle's unpad-paren to unpad all parentheses that are not included
by pad-header, pad-oper, and pad-comma.

x86: Fix flush RSB

The previous assembly is syntactically wrong and managed to somehow not get tested
originally

x86: Helpers for using the speculation MSRs

x86: Define MSRs for speculation control

These MSRs provide access to the IBRS feature and the IBPB command

x86: Helper for flushing RSB

x86: MSR for IA32_ARCH_CAPABILITIES and CPUID flag

Adds definitions for the IA32_ARCH_CAPABILITIES msr, as well as the CPUID leaf that
contains the feature flag for its existance.

x64: add MODIFIES statements for extern functions

The CParser can't deduce modifies rules for functions without
definitions (like in8, out8 et al and interrupt handler functions).
This adds explicit modifies rules for these functions.

SMP: Introduce ENABLE_SMP_SUPPORT

- Make it more readable and less confusing compared to the 'CONFIG_MAX_NUM_NODES > 1' check

Replace Arch_handleInterrupt with Arch_finaliseInterrupt

x86: Handle pending interrupt before scheduling thread in handleSyscall

In handleSyscall the current thread may be preempted to handle a pending interrupt.
With kernel mode interrupts in x86 this handling was delayed until we were about
to switch back to user mode. This change unifies the handling with ARM, where the
interrupt is handled prior to calling the thread scheduler.

SMP: guard arch_pause() with #ifdef for verification purposes

[STYLE_FIX]

SMP: move lock.h to architecture-independent include/smp

s/__sync_lock_test_and_set/__atomic_exchange_n in lock.h

x86: Add Skylake-related info

x86: Load actual EFER MSR on vmexit

Previously we threw away any modifications the kernel may have made
to the EFER when a VM exit happens. In x86-64 there are modifications
to the EFER that must be preserved

x86: Avoid writing the fs/gs base if we don't have to

x64: Support multiple kernel stacks

Adds support for per-core kernel stacks through the use of
thread local storage and swapgs. In addition to the main
kernel stack the IRQ stack also needs to be made per core

[STYLE_FIX]

x86: export tsc freq in bootinfo

We read the frequency from the platform info MSR and export it to the
user for accurate timing (for platforms that support platform into)

[STYLE_FIX]

SELFOUR-287: 32-bit vt-x implementation

This is an implementation of vt-x for x86 kernels running in
ia32 mode.

SELFOUR-632: implement cores non-architecture dependent structres

SELFOUR-499: X86, ARM: Add userspace invocations for hardware debugging

This commit implements the body of SELFOUR-499. The API exposes the x86 DR0-7
and ARM coprocessor 14 features to userspace by virtualizing them as context-
switched registers in the TCB. Implemented as TCB invocations. This feature is
only built when CONFIG_HARDWARE_DEBUG_API is selected.

* Add low-level support routines for setting, unsetting, getting, enabling
and disabling breakpoints.
* Add support for single-stepping as well.
^ Single-stepping is not supported on ARMv6 since the hardware
doesn't have support.
^ ARM implements single-stepping as instruction breakpoints
configured to fault on every instruction -- this is achieved through
the "mismatch" mode, which is only supported from ARMv7 onwards.
* Also support explicit software break requests, a la "BKPT" and "INT $3".

* New invocations:
* seL4_TCB_SetBreakpoint().
* seL4_TCB_GetBreakpoint().
* seL4_TCB_UnsetBreakpoint().
* seL4_TCB_ConfigureSingleStepping().
* New constants:
^ Event types:
^ seL4_InstructionBreakpoint.
^ seL4_DataBreakpoint.
^ seL4_SoftwareBreakRequest.
^ Access types:
^ seL4_BreakOnRead.
^ seL4_BreakOnWrite.
^ seL4_BreakOnReadWrite.
^ Exports:
^ seL4_NumHWBreakpoints.
^ seL4_NumExclusiveBreakpoints.
^ seL4_NumExclusiveWatchpoints.
^ seL4_NumDualFunctionMonitors.
^ seL4_FirstBreakpoint.
^ seL4_FirstWatchpoint.
^ seL4_FirstDualFunctionMonitor.

See documentation in the seL4 API manual.

Revert "Merge pull request #358 in SEL4/sel4 from ~AZARRABI/sel4:multicore to master"

This reverts commit ce2f666bb811c5e4c779829fcb09d5a189ebcdbb, reversing
changes made to dc183f96b81f2344d7d0d910fc430f924eaae940.

Revert "[STYLE_FIX]"

This reverts commit d29f743bbcc3acff2f61b40dedb4fe0839db38b8.

[STYLE_FIX]

SELFOUR-630:preliminary booting application processors
- update core detection code and Kconfig file
- update kernel stack managment so that BSP does not use boot stack before IPI APs
- move arch dependant data to a single structure
- add cache line size to Kconfig
- add cpu indexing and apic id mapping
- boot APs to halting state
- add guard for kernel stack if there is only one core

x86: Fix cpuid family/model composition

Fixes a bug where previously MODEL_ID() was defined as:
`#define MODEL_ID(x) ( ((x & 0xf0000) >> 16) + (x & 0xf0) )`

This was incorrect because (1) it didn't take into account the conditional
nature of the extended_model_ID, and (2) it's actually shifting the
extended_model_ID into the low bits and keeping the model_ID in the high bits,
when it should be the other way around.

This patch also introduces a foundation for more sane testing of CPU vendor,
family, model and brand_ID.

x86: Add missing CPUID functions

x86: Add XSS MSR definition

x86: Define Additional MSRs

Define these MSRs in preparation for their use on the x86_64 port

x86: Improve translation invalidation

x86_64 (with PCIDs enabled) supports a more fine grained invalidation
approach for the TLB and Page Structure Cache. This change expands
the number and kinds of information passed for certain invalidations,
and provides an implementation of this for ia32.

x86: FS/GS base MSRs

when FS/GS_BASE_MSR are used to set the base addreses,
user applications should not touch FS/GS regiters; so
the kernel should load proper selectors once, establishing
limits and other attributes for the segments.

x86: Do not use A constraint in inline assembly as it does not work correctly between 32 and 64 bit code

x86: Move getFaultAddr to general hardware.h, as the read_cr2 is already specialized by the machine mode

x86: Move general x86 functions to common header

x86: Make parts of what have become 32-bit specific headers common

The reason these were not made common to begin with is so that there
was a commit that was just a rename of these files to make any merges
with other branches that might exist easier

x86: Minimal changes to fix previous commit that renamed headers

unsigned int -> word_t

Added a wordRadix constant to x86 kernel.

x86: Make x86 the name of the architecture instead of IA32

IA32 is 32bit version of the x86 architecture. Whilst only IA32
is supported, much of the code is generic x86. Using a generic
x86 architecture will aid in future 64bit support