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512a0200 |
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19-Mar-2020 |
Qian Ge <qian.ge@data61.csiro.au> |
replacing all ifndef with pargma once All the kernel header files now use pargma once rather than the ifndef, as the pre-processed C files do not change while header files are protected with pargma once. This will also solve any naming issues caused by ifndef.
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79da0792 |
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01-Mar-2020 |
Gerwin Klein <gerwin.klein@data61.csiro.au> |
Convert license tags to SPDX identifiers This commit also converts our own copyright headers to directly use SPDX, but leaves all other copyright header intact, only adding the SPDX ident. As far as possible this commit also merges multiple Data61 copyright statements/headers into one for consistency.
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f6e5e218 |
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20-Mar-2019 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
Remove symlinked libsel4 files from include dir These files can be included normally using libsel4 include paths. This removes situations where the same file is available under different include paths due to symlinking into different directory structures.
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d0930f67 |
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18-Mar-2019 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
style: consistently attach return type Add attach-return-type to astyle
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df440f4f |
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13-Apr-2018 |
Yanyan Shen <yanyan.shen@data61.csiro.au> |
armv8/hyp: Read/write MDCR_EL2 for debug control
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40c61e5c |
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18-Jun-2017 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
Fix licenses (the rest)
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c5b52b04 |
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02-Apr-2017 |
Bamboo <bamboo@keg.ertos.in.nicta.com.au> |
[STYLE_FIX]
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4b491dcf |
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23-Mar-2017 |
Kofi Doku Atuah <kofidoku.atuah@data61.csiro.au> |
SELFOUR-836: arm-hyp: Config option for saving/loading vs trapping debug state Provides a configuration option for enabling HDCR.TD* traps, or saving and loading debug state on VCPU switches. Currently verification only plans to support the trap setting. As this option complicates all of the #ifdef's related to debug registers even further, abstractions for enabling/disabling each individual piece of the debug code for different configuration options are also implemented. Part of these refactored #ifdef guards was to remove the guards completely from libsel4 around the definitions of the number of breakpoints and watchpoints.
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3cbe825a |
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23-Mar-2017 |
Kofi Doku Atuah <kofidoku.atuah@data61.csiro.au> |
SELFOUR-836: arm: Correctly trap all debug events We were previously using UNPREDICTABLE behaviour, because we were setting HDCR.TDE without setting the other debug-related bits in HDCR. Also, don't duplicate code: just call setHDCRTrapDebugExceptionState within initHDCR().
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3f90fad6 |
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21-Mar-2017 |
Kofi Doku Atuah <kofidoku.atuah@data61.csiro.au> |
SELFOUR-836: Hardware debug API functions should take tcb_t and not arch_tcb_t Touches files all throughout x86 (32 and 64) and ARM.
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725d0dac |
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20-Mar-2017 |
Kofi Doku Atuah <kofidoku.atuah@data61.csiro.au> |
SELFOUR-836: Disable debug context save/restore between VMs This patch disables the debug register state save and restore on ARM-hyp, such that Guest VMs can now interfere with one another and trigger one another for certain limited scenarios. This will be undone later on.
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f12f0477 |
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27-Feb-2017 |
Kofi Doku Atuah <kofidoku.atuah@data61.csiro.au> |
Add PL0 debug-API support for hyp-mode kernel This patch enables the hype-mode kernel to intercept non-secure PL0 debug exceptions. Since it uses the HDCR register to do this (and not the SDCR), it consequentially has no effect on any secure-monitor that may be executing alongside the hypmode kernel. For native seL4-hyp user threads, when the CPU sees a need to raise a debug exception that was taken from PL0 (user), it will naturally try to raise that exception to PL1 (supervisor). But since seL4 is in PL2 and not PL1, seL4 has not set up an exception vector table (VBAR) for PL1. So when the CPU attempts to vector into the PL1 VBAR, it just gets a data abort, which it then delivers to PL2. This patch causes the PL2 seL4 hypervisor to directly catch the debug exception straight from PL0 and process the debug exception directly, for native threads. Guest VM VCPUs are unaffected by this change. Their debug exceptions are delivered to the Guest VM's PL1 VBAR as per usual.
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469bdd61 |
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04-Jan-2017 |
Kofi Doku Atuah <kofidoku.atuah@data61.csiro.au> |
ARM-HYP: Add support for save/restore of debug registers As things are now, the Guest VMs can modify the debug registers at will from non-secure PL1, and the kernel does nothing to ensure that guest VM debug coprocessor registers are preserved. This is a preliminary patch that simply hooks into vcpu_save and saves the CPU's debug coprocessor registers when saving VCPU state. For restoring the debug registers on switching to a VCPU, we just re-use restore_user_debug_context, which is already called in restore_user_context. (Restore_user_context is called by c_handle_vcpu_fault()). Specifically, we modify the used_breakpoints_bf so that restore_user_debug_context() will always pop all the debug context. This patch only covers the breakpoint and watchpoint registers, and it doesn't cover the entire debug coprocessor, which is another conversation.
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eccaae51 |
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20-Feb-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
s/D61/DATA61/ in license headers for consistency
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bebfcf6d |
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23-Jun-2016 |
Kofi Doku Atuah <kofi.dokuatuah@nicta.com.au> |
SELFOUR-499: X86, ARM: Add userspace invocations for hardware debugging This commit implements the body of SELFOUR-499. The API exposes the x86 DR0-7 and ARM coprocessor 14 features to userspace by virtualizing them as context- switched registers in the TCB. Implemented as TCB invocations. This feature is only built when CONFIG_HARDWARE_DEBUG_API is selected. * Add low-level support routines for setting, unsetting, getting, enabling and disabling breakpoints. * Add support for single-stepping as well. ^ Single-stepping is not supported on ARMv6 since the hardware doesn't have support. ^ ARM implements single-stepping as instruction breakpoints configured to fault on every instruction -- this is achieved through the "mismatch" mode, which is only supported from ARMv7 onwards. * Also support explicit software break requests, a la "BKPT" and "INT $3". * New invocations: * seL4_TCB_SetBreakpoint(). * seL4_TCB_GetBreakpoint(). * seL4_TCB_UnsetBreakpoint(). * seL4_TCB_ConfigureSingleStepping(). * New constants: ^ Event types: ^ seL4_InstructionBreakpoint. ^ seL4_DataBreakpoint. ^ seL4_SoftwareBreakRequest. ^ Access types: ^ seL4_BreakOnRead. ^ seL4_BreakOnWrite. ^ seL4_BreakOnReadWrite. ^ Exports: ^ seL4_NumHWBreakpoints. ^ seL4_NumExclusiveBreakpoints. ^ seL4_NumExclusiveWatchpoints. ^ seL4_NumDualFunctionMonitors. ^ seL4_FirstBreakpoint. ^ seL4_FirstWatchpoint. ^ seL4_FirstDualFunctionMonitor. See documentation in the seL4 API manual.
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3fc76c25 |
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15-Jan-2016 |
amrzar <azarrabi@nicta.com.au> |
Rearranging headers for aarch32 to 32/mode/*
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dc147f8d |
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27-Oct-2015 |
Matthew Fernandez <matthew.fernandez@nicta.com.au> |
ARM: Fix uninitialised variables. This commit fixes two functions where a branch to the default case of a switch statement returns an uninitialised value.
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91b7da86 |
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17-Jul-2014 |
TrusthworthySystems <gatekeeper@sel4.systems> |
Release snapshot
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