History log of /seL4-refos-master/kernel/include/arch/arm/arch/machine.h
Revision Date Author Comments
# 512a0200 19-Mar-2020 Qian Ge <qian.ge@data61.csiro.au>

replacing all ifndef with pargma once

All the kernel header files now use pargma once rather than the ifndef,
as the pre-processed C files do not change while header files
are protected with pargma once. This will also solve any naming issues
caused by ifndef.


# 79da0792 01-Mar-2020 Gerwin Klein <gerwin.klein@data61.csiro.au>

Convert license tags to SPDX identifiers

This commit also converts our own copyright headers to directly use
SPDX, but leaves all other copyright header intact, only adding the
SPDX ident. As far as possible this commit also merges multiple
Data61 copyright statements/headers into one for consistency.


# c06df578 02-Feb-2020 Luca(Wei) Chen <Wei@cvluca.com>

ARM: Add support to flush L1 caches

Extend the existing seL4_BenchmarkFlushCaches without modifing the usage
of it. Will be used in sel4bench to measure the cold cache performance.


# 15091664 20-Mar-2019 Curtis Millar <curtis.millar@data61.csiro.au>

Add syscall for setting the current TLS register.

Some platforms and configurations do not allow user code to change the
value of the register used for TLS. On these architectures a syscall can
be used to allow the kernel to update the register on their behalf.

This does not immediately update the value in the user context on many
configurations as the values are only stored in the user context on a
context switch.


# 84e6d4cd 12-May-2019 Sylvain Gauthier <sylvain.gauthier@data61.csiro.au>

Added IRQ routing to specific core for ARM

Add a new syscall, `seL4_IRQControl_GetTriggerCore`, to get a IRQHandler
with specific target core(s) and trigger method. Only available in SMP
mode.


# e3a83035 10-Apr-2019 Anna Lyons <Anna.Lyons@data61.csiro.au>

boot: consolidate init_freemem

init_freemem sets up available regions of memory for the hardware that
seL4 is booting on. Previously this function was duplicated across
architectures, with minor duplication.

This change provides a top-level init_freemem suitable for all
architectures.

- arm/riscv: change get_avail_p_reg to return whole p_reg array
- update all architectures to use new init_freemem.
- wrap init_freemem calls with arch_init_freemem for each arch, where
arch_init_freemem sets up the available and reserved regions of memory
which are passed to init_freemem.


# 761006e0 18-Mar-2019 Anna Lyons <Anna.Lyons@data61.csiro.au>

style: consistently align pointer with name

Run astyle with align-pointer=name


# b88d7701 12-Feb-2019 Kent McLeod <Kent.Mcleod@data61.csiro.au>

arm: Rename plat_cleanInvalidateCache

Rename plat_cleanInvalidateCache to plat_cleanInvalidateL2Cache to
indicate that it is a L2 cache maintenance operation only.


# f4f6b156 03-Sep-2018 Mitchell Buckley <mitchell.buckley@data61.csiro.au>

SELFOUR-1491: verification updates

- renamed an architecture label so that it begins with ARM.
- changed setIRQTrigger so that it takes a boolean value instead of an int.
- Arch_decodeIRQControlInvocation converts the second argument (trigger)
to a boolean immediately.


# eb0553fa 27-Jun-2018 Anna Lyons <Anna.Lyons@data61.csiro.au>

SELFOUR-1491: add seL4_IRQCOntrol_GetTrigger

Add a new invocation which allows an irq handler capability to be
obtained with a specific trigger method (edge or level). Obtaining
this capability modifies the GIC state.


# ee28936d 18-Jun-2017 Hesham Almatary <hesham.almatary@data61.csiro.au>

SMP: Introduce ENABLE_SMP_SUPPORT

- Make it more readable and less confusing compared to the 'CONFIG_MAX_NUM_NODES > 1' check


# b8f9dcac 27-Feb-2017 Hesham Almatary <hesham.almatary@data61.csiro.au>

ARM/IRQ: add a function to initialise local IRQ controller for CPUs

Similar to initIRQController(), cpu_initLocalIRQController() has to
be implemented for each platform. For those that are gonna support
SMP, it should be implemented proprely (if required), otherwise
it can be stubbed for single core implementations.


# 50995b4c 15-Feb-2017 Jack Suann <Jack.Suann@data61.csiro.au>

Replace Arch_handleInterrupt with Arch_finaliseInterrupt


# 9f67d21c 14-Feb-2017 Jack Suann <Jack.Suann@data61.csiro.au>

x86: Handle pending interrupt before scheduling thread in handleSyscall

In handleSyscall the current thread may be preempted to handle a pending interrupt.
With kernel mode interrupts in x86 this handling was delayed until we were about
to switch back to user mode. This change unifies the handling with ARM, where the
interrupt is handled prior to calling the thread scheduler.


# d5f8fe01 16-Jan-2017 Hesham Almatary <hesham.almatary@data61.csiro.au>

SMP: guard arch_pause() with #ifdef for verification purposes


# 5845659e 16-Jan-2017 Bamboo <bamboo@keg.ertos.in.nicta.com.au>

[STYLE_FIX]


# af02927b 12-Jan-2017 Hesham Almatary <hesham.almatary@data61.csiro.au>

SMP: move lock.h to architecture-independent include/smp

s/__sync_lock_test_and_set/__atomic_exchange_n in lock.h


# 97bac234 08-Dec-2016 Thomas Sewell <Thomas.Sewell@nicta.com.au>

Remove many MODIFIES annotations.

These are redundant for any function which the C-to-Isabelle parser
actually analyses, which is now the vast majority of functions.


# 40383a98 27-Oct-2016 Anna Lyons <Anna.Lyons@data61.csiro.au>

Fix arm builds broken in 44ed6adb6


# 859091b4 04-Aug-2016 Anna Lyons <Anna.Lyons@data61.csiro.au>

SELFOUR-519: remove duplicated constants

* rename physBaseMapping to BASE_OFFSET
* because physBaseMapping was only used explicity in a few places
* move duplicated arm definions up a level
- PPTR_TOP
- PADDR_TOP
- BASE_OFFSET


# c5b6a6a5 06-Jun-2016 Anna Lyons <Anna.Lyons@nicta.com.au>

Refactor duplicated code in hardware.h

One copy to rule them all.


# 11720f23 19-May-2016 Yanyan Shen <yanyan.shen@nicta.com.au>

arm-hyp/tk1: fix bugs found during testing


# 3fc76c25 15-Jan-2016 amrzar <azarrabi@nicta.com.au>

Rearranging headers for aarch32 to 32/mode/*


# 0ecff9f3 09-Nov-2015 Adrian Danis <Adrian.Danis@nicta.com.au>

unsigned int -> word_t


# 2d61910e 09-Nov-2015 Adrian Danis <Adrian.Danis@nicta.com.au>

Rename uint32_t -> word_t in any relevant places


# 682374db 10-May-2015 Adrian Danis <Adrian.Danis@nicta.com.au>

arm: Rearrange context switching code to make fastpath and regular code not duplicate functionality


# b62b20f2 20-Feb-2015 akroh <Alexander.Kroh@nicta.com.au>

ARM: Add config options for exporting PMU and ARM generic timer physical count registers to PL0


# 5d439655 01-Sep-2014 Thomas Sewell <Thomas.Sewell@nicta.com.au>

DONT_TRANSLATE more inline asm functions.

The c-parser can now parse these functions, but it does it by
discarding the inline ASM block, creating a misleading and likely
malformed function body. It is better to not translate these
with a DONT_TRANSLATE comment.

This change has been made for the current verification platform
only, and should probably be extended to any other verification
targets as necessary.


# a318446f 07-Jul-2014 TrustworthySystems <gatekeeper@sel4.systems>

Recommit of arm_hyp branch on release snapshot


# 43e1a215 15-Jul-2014 Adrian Danis <Adrian.Danis@nicta.com.au>

arm: Add work around for errata on some Cortex-A15 boards and move errata checking to C code


# 91b7da86 17-Jul-2014 TrusthworthySystems <gatekeeper@sel4.systems>

Release snapshot