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0d355519 |
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18-Nov-2020 |
Curtis Millar <curtis.millar@data61.csiro.au> |
riscv: Implement benchmark log buffer Can now perform benchmarks on the kernel using the log buffer to trace kernel behavior. Signed-off-by: Curtis Millar <curtis.millar@data61.csiro.au>
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ab3d8c44 |
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18-Nov-2020 |
Curtis Millar <curtis.millar@data61.csiro.au> |
riscv: Map devices with large pages on 32 & 64-bit For 64-bit, this adds a 2nd-level page table for mapping devices using 2MiB frames instead of 1GiB frames. The boot mapping and hardware header generator have also been fixed to correctly report the number of large frames needed for devices rather than only reporting the first. The frame size is also specified correctly (rather than assuming mapping with 4KiB frames). This likely fixes an issue whereby only the first 4KiB frame of a device was reserved but the remaining region of that kernel device could be mapped at user level. Signed-off-by: Curtis Millar <curtis.millar@data61.csiro.au>
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79da0792 |
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01-Mar-2020 |
Gerwin Klein <gerwin.klein@data61.csiro.au> |
Convert license tags to SPDX identifiers This commit also converts our own copyright headers to directly use SPDX, but leaves all other copyright header intact, only adding the SPDX ident. As far as possible this commit also merges multiple Data61 copyright statements/headers into one for consistency.
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8f7b168a |
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06-Aug-2019 |
Yanyan Shen <yanyan.shen@data61.csiro.au> |
riscv: Add SMP data Add data for converting logical core ID to hart ID and vice verse.
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897aaf5b |
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01-Apr-2019 |
Siwei Zhuang <siwei.zhuang@data61.csiro.au> |
RISCV: Change 64 bit kernel window mapping to avoid PMP exception. The SBI memory was mapped outside the kernel window. This would trigger an instruction access fault on some hardware, when the bootloader has set up PMP to protect the SBI memory. Instead of protecting a particular memory region, the PMP locks the entire page table entry that covers the region. The PADDR_LOAD and kernel base are adjusted to have the SBI memory included in the kernel window. So that the SBI memory can be mapped as part of the kernel image to a separate page table entry. This also avoids the kernel to allocate untyped memory from the SBI region.
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2112cd6e |
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07-Aug-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
riscv: Explicit single level 2 page table Only a single level 2 page table is now used for mapping the kernel image so this simplifies the state data to only allocate a single PT and removes the now out of date description.
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b14cc44a |
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07-Aug-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
riscv: Statically determine kernel image window mapping Uses a static check to determine whether or not we can use a single 1 GiB mapping for the kernel image area, or if we need an additional PT.
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b9246b16 |
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19-Jul-2018 |
Jesse Millwood <jesse.millwood@dornerworks.com> |
riscv: Made two level page table for kernel mapping This uses a one dimensional page table for the first level and a two dimensional array for the second level such that in a worst case scenario, the entire kernel region could be mapped using second level tables. Co-authored-by: Chris Guikema <chris.guikema@dornerworks.com> Change-Id: Iad62303a0d7c2321d6038ca718888100614f91db
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83ba0847 |
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20-Feb-2018 |
Hesham Almatary <hesham.almatary@unsw.edu.au> |
[SELFOUR-1156] RISC-V Port Experimental release that supports both RV32 and RV64
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