riscv: Fix preprocess failure

The verification doesn't like FPU. Making FPU code invisible to
verification.

Signed-off-by: Siwei Zhuang <siwei.zhuang@data61.csiro.au>

riscv: Update to use per-hart cached FPU state

Use per-hart cached FPU state on RISC-V, align with other architectures.

Signed-off-by: Siwei Zhuang <siwei.zhuang@data61.csiro.au>

riscv: Update rv64 FPU code

The FPU enable/disable state is cached for all architectures, so
the RV64 FPU code is updated accordingly.

Signed-off-by: Yanyan Shen <yanyan.shen@data61.csiro.au>

trivial: Add license

Signed-off-by: Yanyan Shen <yanyan.shen@data61.csiro.au>

riscv: Add FPU functions for RISCV

These functions are called by the arch-independent functions
to save and restore FPU state lazily.

Signed-off-by: Yanyan Shen <yanyan.shen@data61.csiro.au>