Convert license tags to SPDX identifiers

This commit also converts our own copyright headers to directly use
SPDX, but leaves all other copyright header intact, only adding the
SPDX ident. As far as possible this commit also merges multiple
Data61 copyright statements/headers into one for consistency.

Revert "Cache FPU enable state on all platforms"

This reverts commit 186180cf309b365b45c162f7a1f5931f0fc05d7c.

Cache FPU enable state on all platforms

This change broadens the caching of the FPU enable/disable bit from arm
to all platforms to ensure that on x86 time is not wasted on the
fastpath disabling or enabling an already disabled/enabled FPU.

Revert the recent changes to Faster FPU switch

These changes need to be reverted until we can properly test the changes
with all of our hardware online (currently we cannot test on x86
hardware).

This reverts commit a0aeec3b304d16909619bc847197df221c73a0c4.
This reverts commit af0fdc82c23f1e7e3f1e568f6987f5afd0d2150a.
This reverts commit a190a14ecaae688a6b40dd0a699b8f49c2c0631e.

Cache FPU enable state on all platforms

This change broadens the caching of the FPU enable/disable bit from arm
to all platforms to ensure that on x86 time is not wasted on the
fastpath disabling or enabling an already disabled/enabled FPU.

aarch64: update fpsimd_HWCapTest for ARMv8.2

Prior to this commit this check would fail on ARMv8.2 and greater, as
having a bit set after this version does not imply that FPU/SIMD is not
supported.

For ARMv8.2 and above the values of the AdvSIMD/FP bits in
ID_AA64PFR0_EL1 are as follows:

- 0b1111 means FPU/SIMD is not supported.
- 0b0000 means FPU/SIMD is supported except for half-precision floating
point arithmetic.
- 0b0001 means FPU/SIMD is supported including half-precision floating
point arithmetic.

style: set min-conditional-indent to 0

Given we use braces all the time conditional indents do not make code
cleaner.

style: consistently attach return type

Add attach-return-type to astyle

armv8/hyp: Enable FPU in EL0/1 when HYP is on

The disableFpu() for EL2 traps any FPU instruction to EL2 even
if the FPU is enabled for EL0/1 in CPACR_EL1. For EL2, we
use CPTR_EL2 to enable/disable trapping FPU instructions.
Therefore, we enable FPU for EL0/1 by default so that no additional
exceptions will be generated when we enable FPU access in CPTR_EL2.

armv8: Add isFPUEnabledCached for each core

SELFOUR-806: aarch32 - Implement lazy FP save/restore

This commit implements lazy FP save/restore mechanism, required for user threads
when they use the FPU. The following caveats take place:

* Only support synchronous exceptions. No support for asynchronous ones.
* VFP opcodes are used instead of normal instructions to discard compiler warnings/errors.
* Support is limited to specific ARM subarchitectures we support and tested this commit on.
* Disable the FPU by default if users are not using it to avoid channels.
* FPU support is not verified yet.
* Will not work properly if using a VM that's running besides other VMs/threads that are using the FPU.

Fix licenses (the rest)

[STYLE_FIX]

aarch64: FPU lazy context switch