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a00c2c16 |
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17-Sep-2020 |
Curtis Millar <curtis.millar@data61.csiro.au> |
Make kernel log buffer derived from cmake config This removes the explicit CMake configuration for the kernel log buffer and replaces it with a #define that is enabled for the required configurations. Signed-off-by: Curtis Millar <curtis@curtism.me>
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79da0792 |
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01-Mar-2020 |
Gerwin Klein <gerwin.klein@data61.csiro.au> |
Convert license tags to SPDX identifiers This commit also converts our own copyright headers to directly use SPDX, but leaves all other copyright header intact, only adding the SPDX ident. As far as possible this commit also merges multiple Data61 copyright statements/headers into one for consistency.
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fd83c0a3 |
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20-Mar-2019 |
Curtis Millar <curtis.millar@data61.csiro.au> |
Replace IPC_BUF_GLOBALS_FRAME with KERNEL_GLOBALS_FRAME The globals frame no longer serves its original purpose of informing a thread of its IPC buffer address, and instead as a virtual implementation of thread ID registers.
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bc5c7883 |
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19-Feb-2019 |
Yanyan Shen <yanyan.shen@data61.csiro.au> |
arm: Make Arm VCPU states per-node.
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60e2acdb |
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22-Oct-2017 |
Yanyan Shen <yanyan.shen@data61.csiro.au> |
arm/hyp: add support for running multiple ARM VMs This commit saves/restores various control registers that can be modified by guest VM kernels, so seL4 can execute multiple ARM 32-bit VMs multiplexing a single physical core. When the CONFIG_HAVE_FPU option is selected, the commit allows the VMs to use FPU registers and enables lazily saving/restoring FPU registers for the VMs.
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57fa0e0f |
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07-Aug-2017 |
Hesham Almatary <hesham.almatary@data61.csiro.au> |
Share linker.h between architectures
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4b491dcf |
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23-Mar-2017 |
Kofi Doku Atuah <kofidoku.atuah@data61.csiro.au> |
SELFOUR-836: arm-hyp: Config option for saving/loading vs trapping debug state Provides a configuration option for enabling HDCR.TD* traps, or saving and loading debug state on VCPU switches. Currently verification only plans to support the trap setting. As this option complicates all of the #ifdef's related to debug registers even further, abstractions for enabling/disabling each individual piece of the debug code for different configuration options are also implemented. Part of these refactored #ifdef guards was to remove the guards completely from libsel4 around the definitions of the number of breakpoints and watchpoints.
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4e5cc369 |
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21-Mar-2017 |
Kofi Doku Atuah <kofidoku.atuah@data61.csiro.au> |
SELFOUR-836: Debug-API: setup initial debug context in BOOT_CODE A more efficient way of setting up threads' initial context is implemented by this patch: essentially instead of reading the debug coprocessor everytime we create a thread, we read the coprocessor once at boot and then assign those pre-read values when initializing threads.
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712efa63 |
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21-Feb-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
arm_hyp: Use an explicitly invalid PD when there is no user one When the user has no PD in order to schedule them we must still set something as the active PD, just so that they can then fault. Previously when hypervisor was enabled `0` was at as the PD. This worked as platforms typically do not have anything valid, and certainly nothing resembling a page directory, at physical address 0. This assumption is not very clean and unknown physical addresses should not be accessed, so this change adds an explicit PD that is empty that can be switched to.
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e78cdf9b |
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27-Jul-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
SELFOUR-553: Support alternate IPC buffer locations without globals frame This commit adds support for using the ThreadID registers of the ARM MPCore platforms for storing the address of the IPC buffer instead of the globals frame. The choice of using the user readable/writeable ThreadID register is chosen, even though it means the user cannot use it for its own purposes, as it leaves room in the future for doing TLS support in the user read only register, where compilers expect it.
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2a1d1e94 |
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13-Oct-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
arm_hyp: Add lazy vcpu switching
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4491cae5 |
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29-Aug-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
SELFOUR-556: Rationalize BITS vs INDEX_BITS s/PGD_BITS/PGD_INDEX_BITS Current convention is to say that X_BITS is the log base 2 size of an object, not the log base 2 number of indices
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35c50cfd |
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29-Aug-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
SELFOUR-556: Rationalize BITS vs INDEX_BITS s/PD_BITS/PD_INDEX_BITS Current convention is to say that X_BITS is the log base 2 size of an object, not the log base 2 number of indices
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f251953f |
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29-Aug-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
SELFOUR-556: Rationalize BITS vs INDEX_BITS s/PT_BITS/PT_INDEX_BITS Current convention is to say that X_BITS is the log base 2 size of an object, not the log base 2 number of indices
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16c34811 |
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31-Jul-2016 |
Hesham Almatary <hesham.almatary@data61.csiro.au> |
SELFOUR-518: User-level log buffer Remove global ksLog and use KS_LOG_PPTR instead Benchmark - Log buffer: use global page table
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a4ed36a4 |
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07-Jul-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
SELFOUR-555: Rename ksCurCPU->armHSCurVCPU
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5f0ae410 |
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02-Jun-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
arm-hyp: Minor cleanups Cleanup some small licensing, whitespace and configuration details
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6523fe40 |
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21-Feb-2016 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
Correct previous merge
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cfcaf49c |
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31-Jan-2016 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
SELFOUR-399: object sizes and globals frame addr should come from the same source
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86942825 |
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15-Jan-2016 |
amrzar <azarrabi@nicta.com.au> |
Rearranging sources for aarch32 to 32/*
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