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512a0200 |
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19-Mar-2020 |
Qian Ge <qian.ge@data61.csiro.au> |
replacing all ifndef with pargma once All the kernel header files now use pargma once rather than the ifndef, as the pre-processed C files do not change while header files are protected with pargma once. This will also solve any naming issues caused by ifndef.
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79da0792 |
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01-Mar-2020 |
Gerwin Klein <gerwin.klein@data61.csiro.au> |
Convert license tags to SPDX identifiers This commit also converts our own copyright headers to directly use SPDX, but leaves all other copyright header intact, only adding the SPDX ident. As far as possible this commit also merges multiple Data61 copyright statements/headers into one for consistency.
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07f94833 |
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18-Jun-2017 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
libsel4: fix licenses - some were incorrectly marked GPL (libsel4 is BSD) - update NICTA --> DATA61 etc - fix tags D61 --> DATA61 - update year to 2017
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9ca253a3 |
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07-May-2017 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
SELFOUR-879: expose index and entry constants
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bebfcf6d |
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23-Jun-2016 |
Kofi Doku Atuah <kofi.dokuatuah@nicta.com.au> |
SELFOUR-499: X86, ARM: Add userspace invocations for hardware debugging This commit implements the body of SELFOUR-499. The API exposes the x86 DR0-7 and ARM coprocessor 14 features to userspace by virtualizing them as context- switched registers in the TCB. Implemented as TCB invocations. This feature is only built when CONFIG_HARDWARE_DEBUG_API is selected. * Add low-level support routines for setting, unsetting, getting, enabling and disabling breakpoints. * Add support for single-stepping as well. ^ Single-stepping is not supported on ARMv6 since the hardware doesn't have support. ^ ARM implements single-stepping as instruction breakpoints configured to fault on every instruction -- this is achieved through the "mismatch" mode, which is only supported from ARMv7 onwards. * Also support explicit software break requests, a la "BKPT" and "INT $3". * New invocations: * seL4_TCB_SetBreakpoint(). * seL4_TCB_GetBreakpoint(). * seL4_TCB_UnsetBreakpoint(). * seL4_TCB_ConfigureSingleStepping(). * New constants: ^ Event types: ^ seL4_InstructionBreakpoint. ^ seL4_DataBreakpoint. ^ seL4_SoftwareBreakRequest. ^ Access types: ^ seL4_BreakOnRead. ^ seL4_BreakOnWrite. ^ seL4_BreakOnReadWrite. ^ Exports: ^ seL4_NumHWBreakpoints. ^ seL4_NumExclusiveBreakpoints. ^ seL4_NumExclusiveWatchpoints. ^ seL4_NumDualFunctionMonitors. ^ seL4_FirstBreakpoint. ^ seL4_FirstWatchpoint. ^ seL4_FirstDualFunctionMonitor. See documentation in the seL4 API manual.
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bddd804a |
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06-Jan-2016 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
x86: IOAPIC/MSI syscalls Restructure the x86 interrupt handling to allow for a more flexible method of using IOAPIC and MSI interrupts. The essence of this change is to allow for the user to pick, for both IOAPIC and MSIs, which CPU vector to use. Additionally there is future support, in the API, for seL4 to eventually protect MSI interrupts with the vt-d interrupt routing tables. API behaviour for legacy systems using the PIC is preserved Part of SELFOUR-281
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44a522dc |
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18-Aug-2015 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
libsel4: Generate libsel4 definitions from the current ARCH as well as the SEL4_ARCH
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77588998 |
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16-Dec-2015 |
Anna Lyons <Anna.Lyons@nicta.com.au> |
SELFOUR-244: symlink duplicated files from libsel4 into kernel rather than duplicating them, remove sanity target as a result
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5d42d014 |
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09-Nov-2015 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
x86: Do not conditionally compile IRQ controller code, use build/run time checks Guarding code with #ifdef's makes even cursor testing of 'does this code compile' difficult due to code being hidden by the pre-processor. Using config_set in regular C if statements is performant as the compiler can trivially detect dead code at compile time, and at -O1 and above will not even link in symbols referenced by dead code in these blocks, so this will not bloat image size
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4b3ac0e8 |
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07-Sep-2015 |
Stephen Sherratt <Stephen.Sherratt@nicta.com.au> |
Surrounding benchmarking definitions with "#if CONFIG_MAX_NUM_TRACE_POINTS > 0".
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4c2554dc |
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26-Aug-2015 |
Stephen Sherratt <Stephen.Sherratt@nicta.com.au> |
Added support for using multiple tracepoints at the same time.
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914741ea |
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27-May-2015 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
x86: Make x86 the name of the architecture instead of IA32 IA32 is 32bit version of the x86 architecture. Whilst only IA32 is supported, much of the code is generic x86. Using a generic x86 architecture will aid in future 64bit support
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