riscv: Add FPU state in TCB

Add FPU state storage in TCB and increase TCB size bits when FPU
is enabled.

Signed-off-by: Yanyan Shen <yanyan.shen@data61.csiro.au>

riscv: Fixup EXCEPTION_MESSAGE definition

The seL4_UserException_Number field of the seL4_UserException_Msg is set
explicitly in setMRs_fault with the saved value of scause from when the
exceptioin was taken.

Signed-off-by: Kent McLeod <Kent.Mcleod@data61.csiro.au>

riscv: Remove encoding.h

encoding.h was for ISA simulators originally. It's copied from
riscv-tools which is deprecated. It becomes difficult to maintain the
file. Besides, we merely need 6 lines of code out of this large file. So
redefine what we need in hardware.h and remove encoding.h

replacing all ifndef with pargma once

All the kernel header files now use pargma once rather than the ifndef,
as the pre-processed C files do not change while header files
are protected with pargma once. This will also solve any naming issues
caused by ifndef.

Convert license tags to SPDX identifiers

This commit also converts our own copyright headers to directly use
SPDX, but leaves all other copyright header intact, only adding the
SPDX ident. As far as possible this commit also merges multiple
Data61 copyright statements/headers into one for consistency.

mcs: Timeout fault and reply for RISC-V

Add fault and reply for timeout faults on RISC-V.

mcs: Select additional registers for RISC-V

mcs requires an additional 2 registers for performing system calls to
pass information regarding the reply capability and the destination of a
nbsend/recv.

Fix RISC-V registers to reflect calling convention

Consistent naming of FaultIP and NextIP in kernel

Always refer to the virtual register that stores the address of a fault
as FaultIP and the register that stores the return for a fault NextIP.

style: consistently attach return type

Add attach-return-type to astyle

style: consistently align pointer with name

Run astyle with align-pointer=name

riscv: make register size equal to word size

RISCV32 registers aren't 64 bits wide, after all.

riscv: fix incorrect register index

s4 should be 19, not 10

riscv: add remaining registers to user context.

The registers a7, s2-11, and t3-6 were missing from seL4_UserContext.
We also add these to frameRegisters and gpRegisters, which are used
to implement the TCB invocations for reading and writing these
registers.

Zero-length arrays aren't valid expressions or types in ISO C, so
to keep the c parser happy we need to either remove gpRegisters or
provide some contents for it.

In the past, frameRegisters and gpRegisters distinguished between
those registers preserved across a syscall and those that weren't.
TCB_CopyRegisters allows the caller to choose which set to copy.

Since we preserve all non-return registers, this distinction isn't
relevant anymore and there's no easy way to justify the members of
frameRegisters and gpRegisters.

We arbitrarily choose to put the 'last' register t6 in gpRegisters,
for consistency with the register list in registerset.h and with the
order that registers are restored.

riscv: Define TLS_BASE

Defines TLS_BASE to the be the TP register. Currently the TP register is already used to
place the location of the IPC buffer into it and so a user thread should not set a value
for TLS_BASE unless they have their own way to find their IPC buffer.

riscv: Remove unused register arrays

These arrays use to exist but are no longer used and array definitions such as
SYSCALL_MESSAGE are the new norm. As these have no meaning they are being deleted
to reduce confusion.

riscv: Remove currently unsupported FPU

riscv: correct typo in comment

riscv: remove HARTID

RISCV: Place TODOs in the source

[SELFOUR-1156] RISC-V Port

Experimental release that supports both RV32 and RV64