#
512a0200 |
|
19-Mar-2020 |
Qian Ge <qian.ge@data61.csiro.au> |
replacing all ifndef with pargma once All the kernel header files now use pargma once rather than the ifndef, as the pre-processed C files do not change while header files are protected with pargma once. This will also solve any naming issues caused by ifndef.
|
#
79da0792 |
|
01-Mar-2020 |
Gerwin Klein <gerwin.klein@data61.csiro.au> |
Convert license tags to SPDX identifiers This commit also converts our own copyright headers to directly use SPDX, but leaves all other copyright header intact, only adding the SPDX ident. As far as possible this commit also merges multiple Data61 copyright statements/headers into one for consistency.
|
#
81316c5b |
|
18-Jun-2019 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
cortex-a8: fix check_export_pmu - read PMUSERENR_ENABLE first before updating. On the cortex-a8 (specifically omap3) not doing this would result in the kernel aborting. - do not read DBGDSCR_ext on cortex-a8, read DBGDSCR_int. This is only implemented in armv7.1, not armv7, and also causes the kernel to abort.
|
#
f16b8e22 |
|
17-Jun-2019 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
armv7: enable readDscrCp if ENABLE_BENCHMARKS=y In order to enable user-level access to the PMU, which is required by the benchmarks.
|
#
d0930f67 |
|
18-Mar-2019 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
style: consistently attach return type Add attach-return-type to astyle
|
#
40c61e5c |
|
18-Jun-2017 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
Fix licenses (the rest)
|
#
8f7f8502 |
|
08-Mar-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
SELFOUR-712: arm: enable user level PMU event counter on v7
|
#
eccaae51 |
|
20-Feb-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
s/D61/DATA61/ in license headers for consistency
|
#
19b89ed1 |
|
14-Jan-2017 |
amrzar <azarrabi@nicta.com.au> |
ARM: Add 32 bit directory for armv8-a
|
#
33a771d3 |
|
12-Jul-2016 |
Anna Lyons <Anna.Lyons@nicta.com.au> |
Split fault types into arch/generic Prior to this commit faults were separate per architecture. This commit extracts the common fault types and introduces arch specific faults, reducing code duplication across architectures.
|
#
b90238d0 |
|
19-Oct-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
Replace #pragma once with include guards
|
#
bebfcf6d |
|
23-Jun-2016 |
Kofi Doku Atuah <kofi.dokuatuah@nicta.com.au> |
SELFOUR-499: X86, ARM: Add userspace invocations for hardware debugging This commit implements the body of SELFOUR-499. The API exposes the x86 DR0-7 and ARM coprocessor 14 features to userspace by virtualizing them as context- switched registers in the TCB. Implemented as TCB invocations. This feature is only built when CONFIG_HARDWARE_DEBUG_API is selected. * Add low-level support routines for setting, unsetting, getting, enabling and disabling breakpoints. * Add support for single-stepping as well. ^ Single-stepping is not supported on ARMv6 since the hardware doesn't have support. ^ ARM implements single-stepping as instruction breakpoints configured to fault on every instruction -- this is achieved through the "mismatch" mode, which is only supported from ARMv7 onwards. * Also support explicit software break requests, a la "BKPT" and "INT $3". * New invocations: * seL4_TCB_SetBreakpoint(). * seL4_TCB_GetBreakpoint(). * seL4_TCB_UnsetBreakpoint(). * seL4_TCB_ConfigureSingleStepping(). * New constants: ^ Event types: ^ seL4_InstructionBreakpoint. ^ seL4_DataBreakpoint. ^ seL4_SoftwareBreakRequest. ^ Access types: ^ seL4_BreakOnRead. ^ seL4_BreakOnWrite. ^ seL4_BreakOnReadWrite. ^ Exports: ^ seL4_NumHWBreakpoints. ^ seL4_NumExclusiveBreakpoints. ^ seL4_NumExclusiveWatchpoints. ^ seL4_NumDualFunctionMonitors. ^ seL4_FirstBreakpoint. ^ seL4_FirstWatchpoint. ^ seL4_FirstDualFunctionMonitor. See documentation in the seL4 API manual.
|