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2e3a1bf2 |
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20-Apr-2005 |
Mike Gordon <mjcg@cl.cam.ac.uk> |
Lots of changes aimed at partially automating the adding of new HOL
and Verilog unary and binary operators to synthesis. Read about
AddUnop, AddBinop in README and see how they are used in Fact.ml and
Fact32/Fact32.ml
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