Fix ARM/v4 example for tight equality

The overloading Tw is now temporary within wordsTheory.

Adopt ML-style syntax for case expressions and use freed up "||" for bitwise-or. See issue #24.

Removed trailing whitespace from all .sml and .sig files.

This affects over 900 files and was done using emacs's delete-trailing-whitespace
function in batch mode. Building the system with Poly/ML and Moscow ML seems to
work, so I'm hoping these changes don't break anything. Please complain if
they do!

Repairs: replacing "$-"` with "-".

Test out using using unadorned underscores in case statements.

Also added derived theorems for "ADD rd, pc, #n" and "SUB rd, pc, #n".

Minor tweaks to improve the presentation of ARM_MSR and ARM_SBC theorems.

Renamed bsubst to update (as it is in v4T).

Moved a few definitions/theorems to better homes.

Have rationalised the treatment cases for words,
changing word_nchotomy to ranged_word_nchotomy.

This means that "Cases" and "Cases_on" now subsume
"wordsLib.Cases_word" and "wordsLib.Cases_on_word".
Have eliminated some occurrences of the latter.

Revised expressions of the form <term>:<type> ' <term> to be (<term>:<type>) ' <term>
to avoid confusion with the type variable ' .

Fixed broken proofs - following addition of WORD_ss to srw_ss().

Also replaced %% with '.

Added PC relative STR and LDR.

Fix parsing/printing for UMULL etc.

examples/elliptic/arm -> examples/ARM/v4
examples/arm6 -> examples/ARM/arm6-verification