trivial: move MS_IN_S to utils.h

Update MS_IN_S to be llu

If verification ever see this constant the proofs are much nicer if the
type is specified.

trivial: s/MS_PER_S/MS_IN_S

This is consistent with time defintions on the new-rt branch of the
kernel.

riscv: add cycle count for scheduling timer.

This commit adds a cmake variable for the Clock Frequency used
in the rdtime instruction, which is used for the scheduling tick.

The resetTimer and initTimer functions were updated to use a
calculated cycle count, which is based on the clock frequency and
the timer tick variable.

Change-Id: I130013003ed2c4aec8d5d294624413ee05477d58

riscv: Define explicit functions for registers

Replaces (read|write|set|clear)_csr macros with explicit functions. This provides a boundary
for verification to reason about the operation.

RISCV: Update #ifdef to test compiler variable

The previous config variable wasn't set by CMake. Testing the compiler
variable is more consistent with all other checks.

riscv: Remove todos

This have been converted to JIRA issues.

riscv: remove dev_pregs

We don't have any devices currently, and in future they will be
discovered, not statically specified.

riscv: Fill physical memory regions from FDT

Removes the hardcoded physical memory region from the spike platform and fills it from
FDT parsing instead.

riscv: Prevent race with acking timer interrupt

riscv: Return something from get_dev_p_reg

This function will not actually get called due to get_num_dev_p_regs
returning 0, but it still needs a valid implementation.

riscv: Remove dead definitions

riscv: Document spike memory map limitations

RISC-V: Port FDT from riscv-pk (priv-1.10)

riscv: Remove race in setting timeout

This platform *only* runs on a simulator and so no guarantee can be made in running
fast enough to set the timeout before too much time passes.

RISCV: Place TODOs in the source

[SELFOUR-1156] RISC-V Port

Experimental release that supports both RV32 and RV64