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43b4c551 |
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06-Jan-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x86: Separate definition for kernel vspace root Introduces a separate definition for vspace root that the kernel runs on. Having this be distinct from the global vspace root allows for potential future distinction between the global root (that is copied into all user address spaces) and the address space that the kernel runs in.
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ee28936d |
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18-Jun-2017 |
Hesham Almatary <hesham.almatary@data61.csiro.au> |
SMP: Introduce ENABLE_SMP_SUPPORT - Make it more readable and less confusing compared to the 'CONFIG_MAX_NUM_NODES > 1' check
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40c61e5c |
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18-Jun-2017 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
Fix licenses (the rest)
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93cc22b2 |
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09-Mar-2017 |
amrzar <azarrabi@nicta.com.au> |
smp: fix bugs when stalling remote core - Restart TCB from inside the lock if it is waiting for anything other than IRQ - Only replace the TCB with idle thread if it is in ThreadState_RunningVM state Also, this makes the design generic to be shared with arm.
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f42d6363 |
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15-Mar-2017 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
refactor: initialise common core state in one place
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b595d71f |
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25-Feb-2017 |
amrzar <azarrabi@nicta.com.au> |
x86: initialize ksActiveFPUState for APs
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eccaae51 |
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20-Feb-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
s/D61/DATA61/ in license headers for consistency
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f10efc60 |
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07-Feb-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x86: Use lower memory region for AP boot code Change AP boot code to use a memory region that is lower down, although also smaller. As long as the boot code can fit in this smaller region booting is more reliable as depending on the machine, bios, firmware and bootloader varying amounts of the low memory will be available.
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cea45cd1 |
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31-Jan-2017 |
Jack Suann <Jack.Suann@data61.csiro.au> |
x86: Handling pending interrupts in kernel mode This commit allows x86 to completely handle a pending interrupt without switching out to user mode. To handle an interrupt on x86 the APIC *must* generate an exception, prior to you being able to acknowledge it. Previously we only allow exceptions (i.e. interrupts) to be generated outside of kernel mode when we are in user mode. This change allows us to 'poll' for an interrupt and transition the APIC whilst in kernel mode by enabling and taking interrupts at carefully defined points. A pending interrupt will be stored by the exception handler, allowing us to then handle the interrupt and acknowledge the hardware APIC. Handling is done by waiting until after we have 'left' the kernel and are about to switch to user mode and then 'entering' the kernel again by jumping to the interrupt entry point. Handling interrupts entirely in kernel mode provides two advantages * It will allow, in the future, the ability to handle kernel interrupts in situations where we need to handle the interrupt before actually performing the hardware switch back to user mode. This case happens where the user thread is using vt-x and so pending interrupts do not generate an interrupt exception, but rather cause an exception to be generated telling the system that there is a pending interrupt * Where there are multiple pending interrupts it is more efficient to avoid additional switches in and out of the user thread Whilst this change does not enable pre-emption points to handle the interrupt before returning out of `handleSyscall` it should be easily implementable with what is provided.
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e9922b74 |
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15-Jan-2017 |
Hesham Almatary <hesham.almatary@data61.csiro.au> |
Unify kernel stack definition/declaration and share it between architecures/modes Rather than defining a kernel stack in random places for each architecure for each mode (32/64) and for single/SMP modes, make the stack definition shareable between all of the above. This is also useful for the future ARM SMP work.
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af02927b |
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12-Jan-2017 |
Hesham Almatary <hesham.almatary@data61.csiro.au> |
SMP: move lock.h to architecture-independent include/smp s/__sync_lock_test_and_set/__atomic_exchange_n in lock.h
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5037717c |
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11-Jan-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x86: Explicitly define kernel stack size This commit changes the previous hard coded 4K kernel stack size to being a configurable power of 2 sized stack
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a1eddc75 |
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23-Nov-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x64: Make boot paging structures `VISIBLE` These structures are used from the boot code in traps.S and must be `VISIBLE` to prevent the compiler removing them
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a0cb9e67 |
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09-Nov-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x64: Support multiple kernel stacks Adds support for per-core kernel stacks through the use of thread local storage and swapgs. In addition to the main kernel stack the IRQ stack also needs to be made per core
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27afc1bd |
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20-Nov-2016 |
amrzar <azarrabi@nicta.com.au> |
x86: add logical id mapping for x2APIC IPI boradcasting
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ffd0f34b |
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08-Nov-2016 |
amrzar <azarrabi@nicta.com.au> |
Clean up x86KScurInterrupt: 1. Remove the locking dependancy on the value of x86KScurInterrupt 2. Remove confusing set/unset of x86KScurInterrupt
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a228c492 |
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30-Oct-2016 |
amrzar <azarrabi@nicta.com.au> |
Incuede TLBBitmap in PD to keep track of cores currently accessing this PD
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25bb9437 |
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24-Oct-2016 |
amrzar <azarrabi@nicta.com.au> |
SELFOUR-635: support for TCB operations This will update TCB invocations to consider multicore environment, this may include: - adds the affinity invocation to transfer TCB between different cores and update TCB structure for core ID - checking the thread/core state before performing TCB operation, e.g. deleting the runnable TCB, etc
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1887ae9d |
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13-Oct-2016 |
amrzar <azarrabi@nicta.com.au> |
Update SMP idle thread handling
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e63be664 |
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30-Sep-2016 |
amrzar <azarrabi@nicta.com.au> |
SELFOUR-631: implement CLH lock and barrier infrastructure
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2cbc7123 |
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28-Sep-2016 |
amrzar <azarrabi@nicta.com.au> |
SELFOUR-630:preliminary booting application processors - update core detection code and Kconfig file - update kernel stack managment so that BSP does not use boot stack before IPI APs - move arch dependant data to a single structure - add cache line size to Kconfig - add cpu indexing and apic id mapping - boot APs to halting state - add guard for kernel stack if there is only one core
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4044e204 |
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21-Sep-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
Revert "Merge pull request #358 in SEL4/sel4 from ~AZARRABI/sel4:multicore to master" This reverts commit ce2f666bb811c5e4c779829fcb09d5a189ebcdbb, reversing changes made to dc183f96b81f2344d7d0d910fc430f924eaae940.
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8ffc3531 |
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21-Sep-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
Revert "[STYLE_FIX]" This reverts commit d29f743bbcc3acff2f61b40dedb4fe0839db38b8.
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d29f743b |
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21-Sep-2016 |
Bamboo <bamboo@keg.ertos.in.nicta.com.au> |
[STYLE_FIX]
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fbc071b4 |
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12-Sep-2016 |
amrzar <azarrabi@nicta.com.au> |
SELFOUR-630:preliminary booting application processors - update core detection code and Kconfig file - update kernel stack managment so that BSP does not use boot stack before IPI APs - move arch dependant data to a single structure - add cache line size to Kconfig - add cpu indexing and apic id mapping - boot APs to halting state - add guard for kernel stack if there is only one core
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