History log of /seL4-l4v-10.1.1/seL4/src/arch/riscv/kernel/boot.c
Revision Date Author Comments
# 4cb1d5df 17-Jun-2018 Adrian Danis <Adrian.Danis@data61.csiro.au>

riscv: Define explicit functions for registers

Replaces (read|write|set|clear)_csr macros with explicit functions. This provides a boundary
for verification to reason about the operation.


# d3c12988 10-Apr-2018 Adrian Danis <Adrian.Danis@data61.csiro.au>

riscv: Remove todos

This have been converted to JIRA issues.


# 0c0a0061 10-Apr-2018 Adrian Danis <Adrian.Danis@data61.csiro.au>

riscv: Place traps in text section

Ensures that the traps are in the text section, and not the boot section, allowing for
kernel memory to be safely reused.


# 76c61025 10-Apr-2018 Anna Lyons <Anna.Lyons@data61.csiro.au>

riscv: remove dev_pregs

We don't have any devices currently, and in future they will be
discovered, not statically specified.


# d50cddde 09-Apr-2018 Anna Lyons <Anna.Lyons@data61.csiro.au>

riscv: remove cryptic printout


# 9569ad05 09-Apr-2018 Adrian Danis <Adrian.Danis@data61.csiro.au>

riscv: Parse the FDT during platform initialization


# a6fb504b 09-Apr-2018 Adrian Danis <Adrian.Danis@data61.csiro.au>

riscv: Remove dtb region from free memory

The DTB output should be preserved both during kernel bootup and ultimately given to the
rootserver. As such we should make sure to not include it as free memory.


# 97691ac4 09-Apr-2018 Adrian Danis <Adrian.Danis@data61.csiro.au>

riscv: Move `init_plat`

The platform should not be initialized till after the cpu has been.


# d373b17d 09-Apr-2018 Adrian Danis <Adrian.Danis@data61.csiro.au>

riscv: Provide dtb region to try_init_kernel

Now that there is a different kernel window we can talk about the physical address of the
dtb and read it through the kernel window to determine it's size. Currently we just pass
the region to try_init_kernel, which does not yet do anything with it.


# f37b8a5c 09-Apr-2018 Adrian Danis <Adrian.Danis@data61.csiro.au>

riscv: Remove smp boot code

The SMP code is incomplete and is confusing to have broken code around.


# 22b050c9 05-Apr-2018 Adrian Danis <Adrian.Danis@data61.csiro.au>

riscv: Redesign kernel window

Restructures the kernel window so that instead of being a single contiguous region with
a single offset to physical memory, it is two such regions. This allows us to use the
larger of the two windows as a window into physical memory, and the second smaller window
as a place to run the kernel image from. Having this additional window allows us to
link the kernel for different physical addresses without needing to change its virtual
address, or change the layout of the kernel window.
There are other ways to achieve this, but this is one of the simplest and matches how
x86-64 implements its kernel window.


# 23d83d6c 04-Apr-2018 Anna Lyons <Anna.Lyons@data61.csiro.au>

riscv: remove capFTMapType

it is not used on riscv


# ecadb60c 03-Apr-2018 Adrian Danis <Adrian.Danis@data61.csiro.au>

riscv: Declare extern in global scope

Prevents a compiler warning


# 93171fcb 03-Apr-2018 Adrian Danis <Adrian.Danis@data61.csiro.au>

riscv: Valid c99 function definitions


# 5aa2f7ee 03-Apr-2018 Adrian Danis <Adrian.Danis@data61.csiro.au>

riscv: Remove dead definitions


# ddf14b49 03-Apr-2018 Adrian Danis <Adrian.Danis@data61.csiro.au>

riscv: Remove broken dtb usage

The dtb output is not available after we have switched to our own kernel window and since
the platform should be moved till after the cpu has been initialized we remove the dtb
usage for now until the kernel window can be fixed such that we can access the dtb


# 6af207a0 21-Feb-2018 Hesham Almatary <hesham.almatary@unsw.edu.au>

RISC-V: Port FDT from riscv-pk (priv-1.10)


# aafa5942 27-Mar-2018 Adrian Danis <Adrian.Danis@data61.csiro.au>

RISCV: Place TODOs in the source


# 83ba0847 20-Feb-2018 Hesham Almatary <hesham.almatary@unsw.edu.au>

[SELFOUR-1156] RISC-V Port

Experimental release that supports both RV32 and RV64