TX1: error on SMP + cpu utilisation tracking

TX1 has multiple interrupts for the PMU, one per core. This is
not currently implemented, and is tracked in SELFOUR-1252. It will
work on 1 core.

armv8: Check TCR_EL2 configuration in init_cpu.

armv8: Add SMP support for aarch64

(1) Use NODE_STATE() to access per-core kernel data.
(2) Allocate kernel stack in src/arch/arm/64/head.S.
(3) Use the TPIDR_EL1 to contain the kernel stack pointer
as well as the logical core ID. The kernel stack must
be 4-KiB aligned, and the lowest 12 bits of TPIDR_EL1
are for the logical core ID.
(4) Define the LD_EX, ST_EX, and OP_WIDTH as "ldxr", "stxr",
and "w".
(5) Add irq_remote_call_ipi and irq_reschedule_ipi

Make TIMER_CLOCK_HZ available in timer.h for ARM

The RT kernel needs this value accessible to common functions.

Move definition of initTimer to be arm specific

initTimer does not exist on x86

arm: Add missing memory fence

Without a release+acquire fence here the compiler may assume that the value of ksNumCPUs
does not change, and essentially elide the loop.

Share linker.h between architectures

SMP: Introduce ENABLE_SMP_SUPPORT

- Make it more readable and less confusing compared to the 'CONFIG_MAX_NUM_NODES > 1' check

SELFOUR-806: aarch32 - Implement lazy FP save/restore

This commit implements lazy FP save/restore mechanism, required for user threads
when they use the FPU. The following caveats take place:

* Only support synchronous exceptions. No support for asynchronous ones.
* VFP opcodes are used instead of normal instructions to discard compiler warnings/errors.
* Support is limited to specific ARM subarchitectures we support and tested this commit on.
* Disable the FPU by default if users are not using it to avoid channels.
* FPU support is not verified yet.
* Will not work properly if using a VM that's running besides other VMs/threads that are using the FPU.

SELFOUR-746: IPI Handler for ARM

ARM/SMP: rename/add IRQ macros to match with x86

SELFOUR-748: ARM - Support local/remote TLB invalidation operations

smp: fix bugs when stalling remote core

- Restart TCB from inside the lock if it is waiting for anything other than IRQ
- Only replace the TCB with idle thread if it is in ThreadState_RunningVM state

Also, this makes the design generic to be shared with arm.

trivial: typos in previous commit

refactor: initialise common core state in one place

[STYLE_FIX]

SELFOUR-744: ARM - preliminary booting of other cores

ARM/IRQ: add a function to initialise local IRQ controller for CPUs

Similar to initIRQController(), cpu_initLocalIRQController() has to
be implemented for each platform. For those that are gonna support
SMP, it should be implemented proprely (if required), otherwise
it can be stubbed for single core implementations.

Remove assumption on 32-bit memory offsets

On 64-bit platforms physical address could be >2^32 offset from a virtual address. This
changes offsets to match the word size of the target architecture

ARM/Boot: initialise private timer, user access and benchmark in CPU context

In SMP context, init_cpu is meant to be called for each CPU, where
initialising private timer, user access and benchmarks (basically CCNT)
are per-CPU operations and involve per-CPU hardware
resources/interrupts.

aarch64: FPU lazy context switch

Verification: Guard getCurrentCPUIndex() with SMP #define

[SELFOUR-744]: Modify head.S to load stacks for each core and implement getCurrentCPUIndex

[STYLE_FIX]

Update init_freemem to check for mode dependant reserve regions

aarch64: Initial implementation

ARM: Refactor how we get/set seL4 kernel stack

This commit makes seL4 hold the stack address on TPIDRPRW register (PL1 only
Thread ID Register, VMSA, see B4.1.150 section of ARMv7-A and ARMv7-R
edition reference manual).

Originally, the kernel stack was (re-)mapped to a fixed kernel virtual address and
on traps sp is loaded with this virtual address. Reason is to shave up some
cycles/instructions on (fast) traps path instead of having two instructions
(loading global variable pointer and then memory-load stack address from
it).

With ARM pipelining getting smart/complex (from ARMv7 onwards), there is
no noticeable difference in performance between the two implementations.
Furthermore, this change makes it easy for SMP to load different stacks
for each core and do CPU ID arithmetic efficiently. It also avoids the
issues involving (re-)mapping stacks for different cores if we
followed the original design.

Note: the main side-effect to this change is that the kernel stack for
ARM is no longer mapped with execute-never attribute.

SELFOUR-499: X86, ARM: Add userspace invocations for hardware debugging

This commit implements the body of SELFOUR-499. The API exposes the x86 DR0-7
and ARM coprocessor 14 features to userspace by virtualizing them as context-
switched registers in the TCB. Implemented as TCB invocations. This feature is
only built when CONFIG_HARDWARE_DEBUG_API is selected.

* Add low-level support routines for setting, unsetting, getting, enabling
and disabling breakpoints.
* Add support for single-stepping as well.
^ Single-stepping is not supported on ARMv6 since the hardware
doesn't have support.
^ ARM implements single-stepping as instruction breakpoints
configured to fault on every instruction -- this is achieved through
the "mismatch" mode, which is only supported from ARMv7 onwards.
* Also support explicit software break requests, a la "BKPT" and "INT $3".

* New invocations:
* seL4_TCB_SetBreakpoint().
* seL4_TCB_GetBreakpoint().
* seL4_TCB_UnsetBreakpoint().
* seL4_TCB_ConfigureSingleStepping().
* New constants:
^ Event types:
^ seL4_InstructionBreakpoint.
^ seL4_DataBreakpoint.
^ seL4_SoftwareBreakRequest.
^ Access types:
^ seL4_BreakOnRead.
^ seL4_BreakOnWrite.
^ seL4_BreakOnReadWrite.
^ Exports:
^ seL4_NumHWBreakpoints.
^ seL4_NumExclusiveBreakpoints.
^ seL4_NumExclusiveWatchpoints.
^ seL4_NumDualFunctionMonitors.
^ seL4_FirstBreakpoint.
^ seL4_FirstWatchpoint.
^ seL4_FirstDualFunctionMonitor.

See documentation in the seL4 API manual.

SELFOUR-421 Introduce explicit device frames and untypeds

Kernel objects cannot be created from device untypeds, with the
exception of frames, which do not get zeroed and cannot be used
as an IPC buffer. Device untypeds additionally cannot be used
in the construction of ASID pools.

This then changes the API to the rootserver (i.e. bootinfo) to
send device untypeds instead of device frames. On ARM these
device untypeds are the same as the previously exported device
frame regions. On x86 PCI scanning is removed and all physical
memory addresses (that are not important for kernel integrity)
are released to the user.

In order to have bits in the frame and untyped caps on ARM the
number of software ASIDs had to be reduced from 2^18 to 2^17,
and the maximum untyped size reduced from 2^31 to 2^30

Provide generic C entry/exit hook routines

It can be deseriable to run code before/after user mode, but
not have to write it in assembly. This commit adds such stubs
that get called as the first/last C code when coming in
and out of the kernel

SELFOUR-551: Remove direct accesses to machine data structures

This commit wraps accesses to the vgic in functions that are marked as
DONT_TRANSLATE and uses a global constant (that is determined at boot time)
for the number of LR registers to prevent loops that have undefined bounds

SELFOUR-448 Benchmark: Track thread's CPU utilisation time

Refactor duplicated code in hardware.h

One copy to rule them all.

arm-hyp: Minor cleanups

Cleanup some small licensing, whitespace and configuration details

SELFOUR-229: add error condition for root task overlapping kernel window on ARM

arm-hyp/tk1: add guards so other plats can compile.

arm-hyp/tk1: make style

arm-hyp/tk1: address review comments.

SELFOUR-446 Benchmark: Track syscall feature

Benchmark feature that currently:
- Keeps track of system calls info
- Start time
- Duration
- Capability type
- Invocation tag
- Log the number of invocations of each system call*
- Log the number of invocations for each capability type per syscall.
- Has 3 new syscalls (dump, reset, get size).
- This new feature uses the existing log buffer (which is 1MiB for x86
and ARM). Since the number of syscall invocations is not
deterministic, the logged number of invocations is limited by the size
of the buffer. I suggested to enable the users to pass their own
user-level buffer, to enable more flexibility, later.
- ENABLE_BENCHMARKS is now a parent config option of trace points and
system call track features, they can't be used at the same time.

arm-hyp/tk1: reserve the SMMU interrupt

arm-hyp/tk1: put iospace caps to bootinfo

arm/tk1: a checkpoint for SMMU implementation

arm_hyp: add file to contain hyp mode inline funcs

machine_pl2.h:
new place for hyp mode inline functions.

boot.c:
replace #ifdef ARM_HYP with config_set(ARM_HYP).

vcpu.h, machine_pl2.h:
add empty functions when ARM_HYP is not defined to
pass compilation.

arm_hyp: add file to contain hyp mode inline funcs

machine_pl2.h:
new place for hyp mode inline functions.

boot.c:
replace #ifdef ARM_HYP with config_set(ARM_HYP).

vcpu.h, machine_pl2.h:
add empty functions when ARM_HYP is not defined to
pass compilation.

SELFOUR-114: remove bootinfo.h duplication

Remove mode dependant codes for initial thread from architecture dependant boot codes

Do not switch to the the root thread until after cpu initialization is done

Change additional int->word_t due to interraction with the C parser to ease verification

Rename uint32_t -> word_t in any relevant places

Removed CONFIG_BENCHMARK config option. All checks for '#ifdef CONFIG_BENCHMARK' replaced with '#if CONFIG_MAX_NUM_TRACE_POINTS > 0'.

ARM: Map the initial thread's IPC buffer and boot info as non-executable.

Note that this also required some irrelevant x86 changes to match function
arguments.

ARM: Add config options for exporting PMU and ARM generic timer physical count registers to PL0

arm: Rename BI_CAP_IT_PD to BI_CAP_IT_VSPACE to match x86 and common boot code

arm: Perform additional cache clean to prevent TLB walker loading garbage entries for first user process

Recommit of arm_hyp branch on release snapshot

Release snapshot