riscv: move virtual memory fence after address space switch

While the RISC-V ISA says to that a VMFENCE before a write to the
satp may be necessary, vm faults occur with this ordering when
running on the Rocket Chip. Placing the VMFENCE after the satp write
resolves these faults.

This is also the ordering used in the RISC-V port of Linux when
switching MMU contexts.

Change-Id: I1ec794651d080a5e7a987fa8b2062dc01daeb683

riscv: Order read/writes before writing sptbr

This instruction is required when more than one thread exists with
different ASIDs. The system will lock up after the first context
switch when running on hardware.

Issue first noticed and fixed by Hesham Almatary
<Hesham.Almatary@cl.cam.ac.uk>

Change-Id: I6eb64df6b584ff7de79c8af30b28bbc7bb234643

riscv: Define explicit functions for registers

Replaces (read|write|set|clear)_csr macros with explicit functions. This provides a boundary
for verification to reason about the operation.

riscv: use one definition of page bits

riscv: Remove currently unuspported SMP code

riscv: move machine functions to machine.h

And add memory barriers while we are at it.

riscv: Correct implementation and usage of setVSpaceRoot

setVSpaceRoot is declared in its function signature as taking a paddr, but neither
its implementation nor its usage respected this. The setVSpaceRoot signature was not
changed as its declared as a machine function and should be a minimal wrapper around
register manipulations and so it does make sense for it to take a paddr

[SELFOUR-1156] RISC-V Port

Experimental release that supports both RV32 and RV64