History log of /seL4-l4v-10.1.1/l4v/proof/refine/ARM/IpcCancel_R.thy
Revision Date Author Comments
# 9646c3a3 24-Jun-2018 Gerwin Klein <gerwin.klein@data61.csiro.au>

Isabelle2018 arm: Refine


# 6b9d9d24 09-Jun-2018 Gerwin Klein <gerwin.klein@data61.csiro.au>

Isabelle2018: new "op x" syntax; now is "(x)"

(result of "isabelle update_op -m <dir>")


# b5cdf470 13-Jun-2018 Gerwin Klein <gerwin.klein@data61.csiro.au>

globally use session-qualified imports; add Lib session

Session-qualified imports will be required for Isabelle2018 and help clarify
the structure of sessions in the build tree.

This commit mainly adds a new set of sessions for lib/, including a Lib
session that includes most theories in lib/ and a few separate sessions for
parts that have dependencies beyond CParser or are separate AFP sessions.
The group "lib" collects all lib/ sessions.

As a consequence, other theories should use lib/ theories by session name,
not by path, which in turns means spec and proof sessions should also refer
to each other by session name, not path, to avoid duplicate theory errors in
theory merges later.


# 2d0baab4 13-Mar-2018 Corey Lewis <corey.lewis@data61.csiro.au>

Proof update for crunch changes


# 0f38e200 25-Feb-2018 Thomas Sewell <Thomas.Sewell@data61.csiro.au>

Many proof repairs.


# 652cbb96 14-Mar-2018 Thomas Sewell <Thomas.Sewell@data61.csiro.au>

Initial proof updates for combinator changes.


# 4601f2a1 06-Feb-2018 Joel Beeren <joel.beeren@data61.csiro.au>

Genericise deletion actions that occur after empty_slot

This patch adds a generic "post_cap_deletion" step that is called by
finalise_slot. Previous to this, the only caps which had actions
required at this stage were IRQHandlerCaps -- it was required that the
IRQ bitmap be updated after the cap itself was removed (as the
invariants state that for any existing IRQHandlerCap, the corresponding
bit in the IRQ bitmap must be set).

By genericising this, we add the capacity for new, arch-specific post
cap deletion actions to occur in the future.


# 2a1beffa 26-Nov-2017 Miki Tanaka <miki.tanaka@nicta.com.au>

arm: update for simple_ko getter/setter


# 3a22487c 24-Nov-2017 Rafal Kolanski <rafal.kolanski@nicta.com.au>

arm: revise scheduler / fastpath / scheduler bitmaps (SELFOUR-242)

Colloquially known as "invert-fastpath".

Update verification efforts on ARM for the following seL4 changes:
- scheduling decisions done in possibleSwitchTo are moved to the
scheduler
- possibleSwitchTo only checks whether the candidate is valid for a
fast switch, not its priority, accepting possible candidates
immmediately as a switch-to scheduler action
- the scheduler checks the candidate against the current thread and
against the bitmaps before making a decision
- attemptSwitchTo and switchIfRequiredTo are gone
- scheduler is now more complicated, and numerous proofs related to it
are rewritten from scratch
- fast path now checks ready queues via the scheduler bitmaps
- L2 scheduler bitmap order reversed for better cache locality

Many iterations between the kernel and verification teams were needed
to get this right.


# 48b3a8b4 04-Oct-2017 Matthew Brecknell <Matthew.Brecknell@data61.csiro.au>

update object and field widths for x64, and remove some magic numbers

In X64 update the following to match the C kernel:
- TCB size-bits (11).
- Endpoint size-bits (4).
- Guard bits (58).
- Message registers.

For all architectures, replace magic numbers with defined constants in
specifications, and as far as possible in proofs:
- tcb_bits in abstract spec.
- tcbBlockSizeBits, cteSizeBits, ntfnSizeBits, epSizeBits in Haskell
spec, Haskell and C refinement proofs.


# 42401684 02-Aug-2017 Joel Beeren <joel.beeren@nicta.com.au>

refine: integrate all architectures


# 796887d9 11-Jul-2017 Alejandro Gomez-Londono <alejandro.gomez@nicta.com.au>

Removes all trailing whitespaces


# 7ad3ef3b 13-Mar-2017 Miki Tanaka <miki.tanaka@nicta.com.au>

wp: update the proofs for the new wp/wpc/wpsimp


# 3db5dd77 16-Feb-2017 Miki Tanaka <miki.tanaka@nicta.com.au>

Refine fix for prepare_thread_delete


# 7657681f 29-Jan-2017 Rafal Kolanski <rafal.kolanski@nicta.com.au>

move refine/* to refine/ARM/*, parametrise over $L4V_ARCH