Improving naming of bit-vector signed division constants.

This renaming introduces incompatibilities:

• words$word_sdiv -> words$word_quot (this is proved to be related to int_quot for a non-zero divisor).
• words$word_srem -> words$word_rem (this is proved to be related to int_rem for a non-zero divisor).
• integer_word$word_sdiv (this is a new constant defined directly in terms of int_div).
• words$word_smod -> integer_word$word_smod (this is now defined directly in terms of int_mod).

Generalise some MIPS floating-point instructions.

The BC1* and C.cond.fmt instructions are no longer specialised to $fcc0 only.

Update MIPS tools to support floating-point operations.

This currently omits support for the floating-point memory operations, such as LDC1 and SDC1. (They should be straightforward to support.)

Update MIPS model to include Mike Roe’s floating-point specification.

Also improve treatment of memory operations (so as to be more similar to the CHERI model).

Small fix.

Update for the latest version of L3.

Changes have been made when exporting operations of the form:

`f : args -> state -> value * state`

If the state is not changed then this is now exported as

`f : args -> state -> value`

If the state is changed but the `value` type is `unit` then it this is now exported as

`f : args -> state -> state`.

Update L3 examples.

Most changes relate to Poly/ML moving to fixed-width integers.

Opening lcsymtacs is no longer necessary.

When casting from a bool to a bit-vector use "v2w" instead of a conditional expression.

Fix for MIPS decompilation.

Basic programs seem to be decompiling now.

Add tool support for the MIPS instructions LWL, LWR, LDL and LDR.

Add support for MIPS instructions SC and SCD.

The MIPS tools were experiencing problems with NOP instructions.

Reported by Brian Campbell.

Update the MIPS example.

The model should detect more instances of branches in the branch delay slot, which is categorised as being unpredictable.

Add some assembly code support for the MIPS tools.

Update the MIPS step tool to support cases when processor exceptions occur in the branch delay slot.

Update the MIPS model to catch more unpredictable cases.

Update for L3 examples.

Fixes a potential problem with the handling of word replicate.

Moves some shared code into stateLib (the register_combinations function).

Some other minor fixes.

Move some shared code into utilsLib.

Fix names used in some exceptions.

Update MIPS model and associated tools.

Update for MIPS model and tools.

Simplifies handling of load/stores. (The tools now no longer attempt to accommodate reverse endian mode.)

Fixes modelling of exceptions occurring for an instruction in the branch delay slot. (This has to be properly processed and flagged using the component CP0.Cause.BD.)

Also fixed errors in the specifications of the MADD, MADDU, MSUB, MSUBU, SWR and SDR instructions. (Thanks to Mike Roe for testing the model.)

Support for ERET MIPS instruction.

Update MIPS model.

Now includes the instructions: MOVN, MOVZ, MUL, MADD, MADDU, MSUB and MSUBU. This extends the model beyond vanilla MIPS III.

Updates for machine-code tools.

Added support for introducing SEP_ARRAY predicates for memory operations (applied to the ARM and M0 models).

Update to the MIPS model.

The decoder is now more strict.

Extend support for MTC0 and MFC0 instructions (MIPS).

Improvements to MIPS tools.

Add MIPS model (and tools) to examples.