Updated Juliano's hardware compilation to work with wordsTheory. There are
now some nasty parser warnings with "===>", "<>" and possibly others.

The dev/booth example was/is broken (I haven't attempted to repair it).

Have updated dev/AES/word8 and Crypto/AES. Perhaps dev/AES should be removed?

The hardware compilation for Crypto/TEA and Crypto/RC6 are now broken.
Updating the Crypto examples should be straightforward. Once done I can
delete src/n_bit.

Lots of changes aimed at partially automating the adding of new HOL
and Verilog unary and binary operators to synthesis. Read about
AddUnop, AddBinop in README and see how they are used in Fact.ml and
Fact32/Fact32.ml

Minor bugfix in vsynth.sml + improved and additional examples.

Small modification to vsynth.sml (added global termToVerilogLib so
that the set of functions to print Verilog can be dynamically
extended).

Added to end of README some documentation of the (currently extremely
tedious) stuff needed to add a new combinational component to the
synthesis engine. Hope to automate this kind of extension in the
future.

Added Fact32/Xor32.ml to illustrate adding 32-bit XOR.