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2bd3ae65 |
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18-Jul-2019 |
Yu Hou <Yu.Hou@data61.csiro.au> |
Trivial: style fix make the style checker happy
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101c34f9 |
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15-Jul-2019 |
Yu Hou <Yu.Hou@data61.csiro.au> |
fix various including problem 1: replace quote includes with bracket includes 2: add missing kernel autoconf 3: remove one unused include
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10117b2a |
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04-Jul-2019 |
Yu Hou <Yu.Hou@data61.csiro.au> |
sel4runtime: include configs since global autoconf is removed, we need to manually add back the kernel config and sel4runtime_Config
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83775384 |
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27-Feb-2019 |
Curtis Millar <curtis.millar@data61.csiro.au> |
Update licence dates.
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0b4e4064 |
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24-Feb-2019 |
Curtis Millar <curtis.millar@data61.csiro.au> |
Make thread methods publically available. Make access to thread ID registers publically inlineable. Add function to set tls_base of current thread. Clarify use of registers in ARMv6 The function to write to tpidr_el0 should not exist for ARMv6. Refer to public version of thread_arch.h Use new TLS base function. Clarify the ARMv6 requirements. Remove additional endif. Make set_tls_base always succeed. sel4runtime_tls_base -> sel4runtime_get_tls_base Fix sel4runtime rename in aarch32
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ee0b227a |
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24-Feb-2019 |
Curtis Millar <curtis.millar@data61.csiro.au> |
Update with changed register use for thread ID. The read/write registers for thread ID is now used for TLS.
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1cedfb34 |
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21-Oct-2018 |
Curtis Millar <curtis.millar@data61.csiro.au> |
Fallback on register if no globals frame.
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951698f0 |
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21-Oct-2018 |
Curtis Millar <curtis.millar@data61.csiro.au> |
Licenses.
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fdae8591 |
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19-Oct-2018 |
Curtis Millar <curtis.millar@data61.csiro.au> |
Add thread-pointer access from ARMv6. The thread pointer is accessed via the aeabi specified `__aeabi_read_tp` function. In the case of ARMv6, the value needs to be read from the TLS_BASE stored in the `seL4_GlobalsFrame`.
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