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c84eb20c |
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20-Jul-2020 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
trivial: Fix compiler warnings - Add missing return statements - Add missing const modifiers - Initialize variables correctly - Remove unused variables - Correct incorrect type definitions - Use correct printf format string types
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7cde4d13 |
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04-May-2020 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
ClockServer: Refactor client-server interface Use the connector definitions to control interface configuration and initialization. Provide an ADL API for creating the ClockServer client-server interface in any component.
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c3eaa43a |
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22-Mar-2020 |
Damon Lee <Damon.Lee@data61.csiro.au> |
ClockServer: Change error codes, add diagnostics This changes the error return codes to conform more to our standards of error codes being negative instead of positive. Also add in error diagnostic messages to help the user investigate errors.
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fc91ddf9 |
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22-Mar-2020 |
Damon Lee <Damon.Lee@data61.csiro.au> |
ClockServer,tx2: Add BPMP connector definitions Instead of initialising the BPMP component alongside the ClockServer, this commit changes it so that the user has to instantiate an instance of the BPMPServer and connect it to the ClockServer. Also, this commit also adds a platform specific initialisation function to allow platform specific initialisation procedures to be carried out before initialising the clock drivers. For the tx2, this involves creating a BPMP interface using the BPMPServer server library and registering it with the interface registration service so that clock driver can find it and use it.
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82d530f0 |
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01-Oct-2019 |
Damon Lee <Damon.Lee@data61.csiro.au> |
components: Add ClockServer component The ClockServer component is a new component that is responsible for managing and multiplexing requests to the clock controllers of a particular platform. The functionality of the component is very limited at the moment and can only support the functionality that is exposed via the clock subsystem in libplatsupport. There is no access control with regards to clock gates so components can interfere with other components by manipulating the clock gates.
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