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96a5894c |
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02-Jul-2020 |
Michael Yoo <Michael.Yoo@data61.csiro.au> |
x86: Fix IF reset upon nested interrupt Fixes interrupt flag reset upon nested interrupt resume. There were intermittent test failures on x86/32 characterised by assertion failures at `c_nested_interrupt()`. The kernel only allows one pending interrupt at a time, yet the kernel was entering `c_nested_interrupt()` multiple times during a single entry-exit. This should have been disallowed by `getActiveIRQ()` checking against any pending interrupts. `c_nested_interrupt()` is "entered" by the pc99-specific `receivePendingIRQ()` helper (i.e. `sti; nop; cli`). If the nested interrupt handler fails to clear the interrupt flag before running `iret`, there's a small window between `nop; cli` that could trigger a second nested interrupt. This fixes the nested interrupt trap to correctly clear the interrupt flag in the EFLAGS register that is restored upon `iret`. Signed-off-by: Michael Yoo <Michael.Yoo@data61.csiro.au>
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79da0792 |
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01-Mar-2020 |
Gerwin Klein <gerwin.klein@data61.csiro.au> |
Convert license tags to SPDX identifiers This commit also converts our own copyright headers to directly use SPDX, but leaves all other copyright header intact, only adding the SPDX ident. As far as possible this commit also merges multiple Data61 copyright statements/headers into one for consistency.
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554f812d |
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08-Nov-2016 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
mcs: scheduling context donation over ipc After this commit, threads blocked on an endpoint can recieve a scheduling context from the thread that wakes the blocked thread.
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fc8f886a |
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01-Jul-2019 |
Curtis Millar <curtis.millar@data61.csiro.au> |
Only reset segments if changed (ia32) Only force a reset of the segments (and a reload from the GDT) if the segment selectors were changed by user-level.
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3207abee |
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20-Mar-2019 |
Curtis Millar <curtis.millar@data61.csiro.au> |
RFC-3: Update context for x86 to use FS and GS. TLS_BASE virtual register is replaced with FS_BASE and GS_BASE virtual registers. The FS_BASE and GS_BASE virtual registers are moved to the end of the context so they need not be considered in the kernel exit and entry implementation. Removed tracking of ES, DS, FS, and GS segment selectors on kernel entry and exit. ES and DS are clobbered on kernel entry with the RPL 3 selector for a DPL 3 linear data segment. FS is clobbered on exit with the RPL 3 selector for the DPL 3 segment with FS_BASE as the base. This is done on exit to reload the value from the GDT. GS is clobbered on exit with the RPL 3 selector for the DPL 3 segment with GS_BASE as the base. This is done on exit to reload the value from the GDT. Kernel entry and exit code is refactored, simplified, and improved in light of the above changes. x64: update verified config to use fsgsbase instr The verification platform for x64 relies on the fsgsbase instruction.
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69339d42 |
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09-Apr-2019 |
Jasper Lowell <jasper.lowell@data61.csiro.au> |
Boot code: Statically allocate idle thread The idle thread is not managed at user-level and so it can instead be statically allocated. This simplifies the boot code and increments towards being easier to formally verify.
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4b7ac35e |
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20-Mar-2019 |
Curtis Millar <curtis.millar@data61.csiro.au> |
Clarify array reference semantics for ia32 This makes it easier to understand what particular accesses to the TCB are occuring via the stack.
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ee28936d |
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18-Jun-2017 |
Hesham Almatary <hesham.almatary@data61.csiro.au> |
SMP: Introduce ENABLE_SMP_SUPPORT - Make it more readable and less confusing compared to the 'CONFIG_MAX_NUM_NODES > 1' check
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7c6fd56b |
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14-Feb-2017 |
Jack Suann <Jack.Suann@data61.csiro.au> |
ia32: Added common exception handler
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c988403c |
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02-Feb-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x86: Enable kernel exceptions in non debug mode that can return to new IP Changes `handleKernelException` to always be called, regardless of debug mode or not and gives `handleKernelException` the ability to return with a new IP that the exception should return to. Currently this feature is not used and `handleKernelException` always performs halt.
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c102eae7 |
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02-Feb-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
ia32: Pop EDI when returning from kernel exceptions Previously ESI was incorrectly being popped twice, presumably a typo
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cea45cd1 |
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31-Jan-2017 |
Jack Suann <Jack.Suann@data61.csiro.au> |
x86: Handling pending interrupts in kernel mode This commit allows x86 to completely handle a pending interrupt without switching out to user mode. To handle an interrupt on x86 the APIC *must* generate an exception, prior to you being able to acknowledge it. Previously we only allow exceptions (i.e. interrupts) to be generated outside of kernel mode when we are in user mode. This change allows us to 'poll' for an interrupt and transition the APIC whilst in kernel mode by enabling and taking interrupts at carefully defined points. A pending interrupt will be stored by the exception handler, allowing us to then handle the interrupt and acknowledge the hardware APIC. Handling is done by waiting until after we have 'left' the kernel and are about to switch to user mode and then 'entering' the kernel again by jumping to the interrupt entry point. Handling interrupts entirely in kernel mode provides two advantages * It will allow, in the future, the ability to handle kernel interrupts in situations where we need to handle the interrupt before actually performing the hardware switch back to user mode. This case happens where the user thread is using vt-x and so pending interrupts do not generate an interrupt exception, but rather cause an exception to be generated telling the system that there is a pending interrupt * Where there are multiple pending interrupts it is more efficient to avoid additional switches in and out of the user thread Whilst this change does not enable pre-emption points to handle the interrupt before returning out of `handleSyscall` it should be easily implementable with what is provided.
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5037717c |
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11-Jan-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x86: Explicitly define kernel stack size This commit changes the previous hard coded 4K kernel stack size to being a configurable power of 2 sized stack
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90f6a986 |
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31-Oct-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x86: Initial support for SMP vt-x Enables vt-x code to compile when CONFIG_MAX_NUM_NODES is set to greater than 1 and adds code to manage VMCS state on different cores
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ffd0f34b |
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08-Nov-2016 |
amrzar <azarrabi@nicta.com.au> |
Clean up x86KScurInterrupt: 1. Remove the locking dependancy on the value of x86KScurInterrupt 2. Remove confusing set/unset of x86KScurInterrupt
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7fbde1bb |
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14-Jun-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
SELFOUR-287: 32-bit vt-x implementation This is an implementation of vt-x for x86 kernels running in ia32 mode.
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bebfcf6d |
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23-Jun-2016 |
Kofi Doku Atuah <kofi.dokuatuah@nicta.com.au> |
SELFOUR-499: X86, ARM: Add userspace invocations for hardware debugging This commit implements the body of SELFOUR-499. The API exposes the x86 DR0-7 and ARM coprocessor 14 features to userspace by virtualizing them as context- switched registers in the TCB. Implemented as TCB invocations. This feature is only built when CONFIG_HARDWARE_DEBUG_API is selected. * Add low-level support routines for setting, unsetting, getting, enabling and disabling breakpoints. * Add support for single-stepping as well. ^ Single-stepping is not supported on ARMv6 since the hardware doesn't have support. ^ ARM implements single-stepping as instruction breakpoints configured to fault on every instruction -- this is achieved through the "mismatch" mode, which is only supported from ARMv7 onwards. * Also support explicit software break requests, a la "BKPT" and "INT $3". * New invocations: * seL4_TCB_SetBreakpoint(). * seL4_TCB_GetBreakpoint(). * seL4_TCB_UnsetBreakpoint(). * seL4_TCB_ConfigureSingleStepping(). * New constants: ^ Event types: ^ seL4_InstructionBreakpoint. ^ seL4_DataBreakpoint. ^ seL4_SoftwareBreakRequest. ^ Access types: ^ seL4_BreakOnRead. ^ seL4_BreakOnWrite. ^ seL4_BreakOnReadWrite. ^ Exports: ^ seL4_NumHWBreakpoints. ^ seL4_NumExclusiveBreakpoints. ^ seL4_NumExclusiveWatchpoints. ^ seL4_NumDualFunctionMonitors. ^ seL4_FirstBreakpoint. ^ seL4_FirstWatchpoint. ^ seL4_FirstDualFunctionMonitor. See documentation in the seL4 API manual.
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2cbc7123 |
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28-Sep-2016 |
amrzar <azarrabi@nicta.com.au> |
SELFOUR-630:preliminary booting application processors - update core detection code and Kconfig file - update kernel stack managment so that BSP does not use boot stack before IPI APs - move arch dependant data to a single structure - add cache line size to Kconfig - add cpu indexing and apic id mapping - boot APs to halting state - add guard for kernel stack if there is only one core
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4044e204 |
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21-Sep-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
Revert "Merge pull request #358 in SEL4/sel4 from ~AZARRABI/sel4:multicore to master" This reverts commit ce2f666bb811c5e4c779829fcb09d5a189ebcdbb, reversing changes made to dc183f96b81f2344d7d0d910fc430f924eaae940.
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fbc071b4 |
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12-Sep-2016 |
amrzar <azarrabi@nicta.com.au> |
SELFOUR-630:preliminary booting application processors - update core detection code and Kconfig file - update kernel stack managment so that BSP does not use boot stack before IPI APs - move arch dependant data to a single structure - add cache line size to Kconfig - add cpu indexing and apic id mapping - boot APs to halting state - add guard for kernel stack if there is only one core
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b648b297 |
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22-May-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x86: Reorder c_handle_syscall arguments
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59d820a0 |
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01-Jul-2015 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
x86: Use standard calling convention instead of fastcall There is no measureable benefit from using the fastcall calling convention and in all but one usage location the compiler should be inlining all the functions calls, making the calling convention completely irrelevant
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74f620d1 |
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29-Jun-2015 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
x86: Rename FaultEIP and NextEIP to FaultIP and NextIP to allow for 32/64-bit independent code
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71a45e6b |
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05-Nov-2015 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
x86: Strip multi kernel support from the x86 kernel. This is not used and is conflicting with planned future features
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198f6c84 |
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01-Jun-2015 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
x86: Move 32-bit specific files into 'mode' directories, and only build if IA32
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