riscv: Reset FPU owner when deleting a thread

If a thread to be deleted is the current FPU owner, we switch
away from the thread.

Signed-off-by: Yanyan Shen <yanyan.shen@data61.csiro.au>

riscv: tweak Arch_isFrameType argument name

It was 'type' on all other arches, but 't' on riscv. Being consistent
here means we can have the same proof for all arches.

Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>

riscv: add ghost state tracking for RISC-V objects

This commit adds ghost state annotations for the creation of pages and
page tables in RISC-V (up to 3-level tables only, because the
verification target currently does not support more.)

Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>

riscv: use word_t rather than "unsigned int"

For other platforms, word_t is used for passing length and size
parameters and adapts to 32 and 64-bit platforms appropriately.
The riscv platforms stands out by using "unsigned int" unlike the
others.

Reduce usage of "unsigned int" to match the other 64-bit verification
target platform, x86 64-bit.

Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>

Convert license tags to SPDX identifiers

This commit also converts our own copyright headers to directly use
SPDX, but leaves all other copyright header intact, only adding the
SPDX ident. As far as possible this commit also merges multiple
Data61 copyright statements/headers into one for consistency.

unify userSize type declarations

Other declarations of `userSize` give it the type `word_t`. Since proofs
use a mangled name that includes the type, giving `userSize` different
types at different locations occasionally breaks proofs.

riscv: make consistent PageTable isMapped checks

A page table cap has at least the following entries:
- capPTMappedASID
- capPTIsMapped
- capPTMappedAddress

These are used to implement a type Option<(ASID, MappedAddress)> where
capPTIsMapped is used to reflect whether the values capPTMappedASID and
capPTMappedAddress are valid or not. Frame caps don't have an IsMapped
equivalent but instead check if capFMappedASID == 0. When a Pagetable
is unmapped capPTIsMapped is cleared, but capPTMappedASID and
capPTMappedAddress are left unchanged. When a frame is unmapped then
capFMappedASID will be set to 0.

It appears that the RISC-V port often uses
cap_page_table_cap_get_capPTMappedASID(cap) != asidInvalid to check
whether a page table cap is mapped. This can lead to incorrect behavior
if a page table has been mapped and then unmapped as the asid will be
left as a valid asid. Each of these changes are changed to instead
consistently check capPTIsMapped. In addition it is required that a when
a PageTable becomes reachable as either a vspace_root, or another entry
in the tree that capPTIsMapped is set.

style: set min-conditional-indent to 0

Given we use braces all the time conditional indents do not make code
cleaner.

style: consistently attach return type

Add attach-return-type to astyle

style: correct parenthesis padding

Use astyle's unpad-paren to unpad all parentheses that are not included
by pad-header, pad-oper, and pad-comma.

riscv: Respect deviceMemory

Passes the `deviceMemory` flag given to `Arch_createObject` into the frame cap instead of
pretending that all frames are valid kernel object memory.

riscv: Do not zero memory in Arch_createObject

It use to be be the responsibility of createObject, and by extension Arch_createObject,
to zero memory if so required. Since the riscv port was originally started the responsiblity
of zering the memory was moved to generic untyped retype handling, however this change
was never propogated to the riscv architecture. As it stands this memory zeroing is
guaranteed to zero memory that was already zeroed, which is just a performance (and proof),
issue and so we want to remove them.

riscv: Add extra device frame check

This check is redundant, but provides a simplification for verification.

riscv: Handle ASID caps in Arch_sameRegionAs

riscv: Handle ASID caps in Arch_finaliseCap

riscv: Mask frame cap rights

Correctly updates cap rights for new cap permissions through an updateCapData call

riscv: use one definition of page bits

riscv: check all frame types in Arch_isFrameType

riscv: finally remove isVTableRoot with last usage

Where and how we use this is context dependent so it is now inlined

riscv: remove capFTMapType

it is not used on riscv

riscv: Remove incorrectly formatted printf

riscv: Simplify Arch_decodeInvocation

riscv only has a single kind of arch invocation, that for MMUs.

riscv: Remove unused function

riscv: Missing arch cap abstractions

These are needed after rebase

RISCV: Place TODOs in the source

[SELFOUR-1156] RISC-V Port

Experimental release that supports both RV32 and RV64