History log of /seL4-camkes-master/kernel/src/arch/riscv/kernel/thread.c
Revision Date Author Comments
# 79da0792 01-Mar-2020 Gerwin Klein <gerwin.klein@data61.csiro.au>

Convert license tags to SPDX identifiers

This commit also converts our own copyright headers to directly use
SPDX, but leaves all other copyright header intact, only adding the
SPDX ident. As far as possible this commit also merges multiple
Data61 copyright statements/headers into one for consistency.


# 99e9092b 06-Aug-2019 Yanyan Shen <yanyan.shen@data61.csiro.au>

riscv: Set up the idle threads' per-core stacks

Use per-core stacks for idle thread stacks.


# b6417f21 20-Mar-2019 Curtis Millar <curtis.millar@data61.csiro.au>

Remove platform IPC buffer register.

This removes the assumption that each platform sotres the IPC buffer
address in a platform-specific register. The IPC buffer address is
instead stored in a thread-local variable in libsel4 which must be
initialised by the runtime.


# 01b73622 27-May-2019 Curtis Millar <curtis.millar@data61.csiro.au>

Consistent naming of FaultIP and NextIP in kernel

Always refer to the virtual register that stores the address of a fault
as FaultIP and the register that stores the return for a fault NextIP.


# f7ba572f 28-Apr-2019 Kent McLeod <Kent.Mcleod@data61.csiro.au>

RISC-V: Use correct sstatus value for idle thread

We were incorrectly enabling interrupts for the current context instead
of the return context. This was causing the hart to be preempted before
an sret call could be performed when switching to the idle thread.


# d0930f67 18-Mar-2019 Anna Lyons <Anna.Lyons@data61.csiro.au>

style: consistently attach return type

Add attach-return-type to astyle


# d419b41c 09-Aug-2018 Curtis Millar <curtis.millar@data61.csiro.au>

Remove attribute for RISCV as well


# bb302553 03-Apr-2018 Adrian Danis <Adrian.Danis@data61.csiro.au>

riscv: Correct stack setting for idle thread

This sets the idle thread to have a stack top, instead of a stack bottom, which means
it no longer needs to have a custom optimize pragma to avoid using the stack.


# 9b0056da 03-Apr-2018 Adrian Danis <Adrian.Danis@data61.csiro.au>

riscv: remove HARTID


# 83ba0847 20-Feb-2018 Hesham Almatary <hesham.almatary@unsw.edu.au>

[SELFOUR-1156] RISC-V Port

Experimental release that supports both RV32 and RV64