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79da0792 |
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01-Mar-2020 |
Gerwin Klein <gerwin.klein@data61.csiro.au> |
Convert license tags to SPDX identifiers This commit also converts our own copyright headers to directly use SPDX, but leaves all other copyright header intact, only adding the SPDX ident. As far as possible this commit also merges multiple Data61 copyright statements/headers into one for consistency.
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99e9092b |
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06-Aug-2019 |
Yanyan Shen <yanyan.shen@data61.csiro.au> |
riscv: Set up the idle threads' per-core stacks Use per-core stacks for idle thread stacks.
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b6417f21 |
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20-Mar-2019 |
Curtis Millar <curtis.millar@data61.csiro.au> |
Remove platform IPC buffer register. This removes the assumption that each platform sotres the IPC buffer address in a platform-specific register. The IPC buffer address is instead stored in a thread-local variable in libsel4 which must be initialised by the runtime.
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01b73622 |
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27-May-2019 |
Curtis Millar <curtis.millar@data61.csiro.au> |
Consistent naming of FaultIP and NextIP in kernel Always refer to the virtual register that stores the address of a fault as FaultIP and the register that stores the return for a fault NextIP.
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f7ba572f |
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28-Apr-2019 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
RISC-V: Use correct sstatus value for idle thread We were incorrectly enabling interrupts for the current context instead of the return context. This was causing the hart to be preempted before an sret call could be performed when switching to the idle thread.
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d0930f67 |
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18-Mar-2019 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
style: consistently attach return type Add attach-return-type to astyle
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d419b41c |
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09-Aug-2018 |
Curtis Millar <curtis.millar@data61.csiro.au> |
Remove attribute for RISCV as well
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bb302553 |
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03-Apr-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
riscv: Correct stack setting for idle thread This sets the idle thread to have a stack top, instead of a stack bottom, which means it no longer needs to have a custom optimize pragma to avoid using the stack.
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9b0056da |
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03-Apr-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
riscv: remove HARTID
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83ba0847 |
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20-Feb-2018 |
Hesham Almatary <hesham.almatary@unsw.edu.au> |
[SELFOUR-1156] RISC-V Port Experimental release that supports both RV32 and RV64
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