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0d355519 |
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18-Nov-2020 |
Curtis Millar <curtis.millar@data61.csiro.au> |
riscv: Implement benchmark log buffer Can now perform benchmarks on the kernel using the log buffer to trace kernel behavior. Signed-off-by: Curtis Millar <curtis.millar@data61.csiro.au>
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5c1b81d9 |
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03-Sep-2020 |
Gerwin Klein <gerwin.klein@data61.csiro.au> |
libsel4: fix license tags These files should have been released under BSD-2-Clause in the first place (as per parent LICENSE.md file). Closes #245 Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
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5a341610 |
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01-Aug-2020 |
Stefan O'Rear <sorear@fastmail.com> |
Do not generate data symbols for enums With clang 11 these become bss symbols rather than commons, resulting in multiple definition errors at link time. gcc 10 is likely to expose the same issue. Signed-off-by: Stefan O'Rear <sorear@fastmail.com>
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0c88f21a |
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14-Apr-2020 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
libsel4,riscv: Remove seL4_UserException_FLAGS This field is unused and is never set to anything by the kernel. Other architecture definitions of seL4_UserException_Msg contain an equivalent field for a current-program-status-register-like register that the fault handler can read and modify as part of fault handling. RISC-V's equivalent register SSTATUS doesn't contain any fields that would be useful for a fault handler to modify at this stage and so the register isn't transferred in the fault. Signed-off-by: Kent McLeod <Kent.Mcleod@data61.csiro.au>
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512a0200 |
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19-Mar-2020 |
Qian Ge <qian.ge@data61.csiro.au> |
replacing all ifndef with pargma once All the kernel header files now use pargma once rather than the ifndef, as the pre-processed C files do not change while header files are protected with pargma once. This will also solve any naming issues caused by ifndef.
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79da0792 |
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01-Mar-2020 |
Gerwin Klein <gerwin.klein@data61.csiro.au> |
Convert license tags to SPDX identifiers This commit also converts our own copyright headers to directly use SPDX, but leaves all other copyright header intact, only adding the SPDX ident. As far as possible this commit also merges multiple Data61 copyright statements/headers into one for consistency.
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2d40b0d5 |
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09-Feb-2020 |
Curtis Millar <curtis.millar@data61.csiro.au> |
riscv32 does not support huge pages For some reason the kernel documented and maintained constants for a 512MiB 'huge page' in riscv32 which is not part of the specification. The references and constants are removed
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97782dcf |
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17-Jul-2019 |
Curtis Millar <curtis.millar@data61.csiro.au> |
mcs: Update size constants for RISC-V Update the notification size constant for the larger notification of MCS and add the constant for the size of the reply object.
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d869b3ad |
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17-Jul-2019 |
Curtis Millar <curtis.millar@data61.csiro.au> |
mcs: Timeout fault and reply for RISC-V Add fault and reply for timeout faults on RISC-V.
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5f8e3615 |
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17-Jun-2019 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
trivial: VspaceBits -> VSpaceBits on riscv32
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f3fbf855 |
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29-Apr-2019 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
libsel4: add seL4_VspaceBits This constant represents the size of the root page table.
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8c17f0f0 |
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10-Apr-2019 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
libsel4,riscv: Hide enums for non-C preprocessing sel4/sel4_arch/constants.h gets used to provide constants in linker files and we want to avoid generation of enum definitions
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142bf9b1 |
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21-Mar-2019 |
Sylvain Gauthier <sylvain.gauthier@data61.csiro.au> |
More standard constant name, moved ASID constants to arch generic files
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5fe6d0bc |
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12-Dec-2018 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
riscv/spike: fix seL4_UserTop for riscv Use correct values and document them.
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76faadc9 |
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06-Dec-2018 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
Add seL4_UserTop and move kernelBase to the arch level - seL4_UserTop is a new constant which represents the top of virtual memory available to user level - this commit also rationalises several constants (USER_TOP, kernelBase) and moves them to the arch level, such that ports only need to define seL4_UserTop.
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1b68590b |
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11-Apr-2018 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
riscv: use one definition of page bits
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0764d2ac |
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04-Apr-2018 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
riscv: build on 32 bit
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05a914b6 |
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03-Apr-2018 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
SELFOUR-1276: set PrefetchFault MR for riscv This was being tracked in the fault_t, but not set as part of the message to the user.
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83ba0847 |
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20-Feb-2018 |
Hesham Almatary <hesham.almatary@unsw.edu.au> |
[SELFOUR-1156] RISC-V Port Experimental release that supports both RV32 and RV64
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