smmuv2: Reserve VSpace slot for holding CB count

A slot in the top level VSpace page table is used to hold the number of
SMMUv2 ContextBanks that are assigned to a VSpace. This means a
reduction of available virtual addresses at userlevel as the slot cannot
be used for holding regular mappings.

Signed-off-by: Kent McLeod <kent@kry10.com>

aarch64,cortex-a53,hyp: Reduce seL4_UserTop value

This ensures that no frames can be mapped that would overwrite the
currently stored VMID for the vspace.

Signed-off-by: Kent McLeod <kent@kry10.com>

Do not generate data symbols for enums

With clang 11 these become bss symbols rather than commons, resulting in
multiple definition errors at link time. gcc 10 is likely to expose the
same issue.

Signed-off-by: Stefan O'Rear <sorear@fastmail.com>

aarch64,vcpu: Add CNTKCTL_EL1 register to vcpu_t

This register is accessible from EL1 and affects whether Generic Timer
registers are accessible from EL0. When switching out of guests, the
kernel needs to restore the correct access for native threads.

Signed-off-by: Kent McLeod <Kent.Mcleod@data61.csiro.au>

fixing missed header files

This is the second commit for replacing ifndef with pargma
once in kernel header files. A few header files are missed
in the first round, hence this commit.

Convert license tags to SPDX identifiers

This commit also converts our own copyright headers to directly use
SPDX, but leaves all other copyright header intact, only adding the
SPDX ident. As far as possible this commit also merges multiple
Data61 copyright statements/headers into one for consistency.

arm: Added define for VMPIDR and VMPIDR_EL2

Added constant definitions for the VMPIDR (arm32) and VMPIDR_EL2
(arm64) registers. These being vcpu registers that can be
written, read, saved and restored. The 'Virtualization Multiprocessor
ID Register' (VMPIDR) is needed to program a vcpu's affinity during
initialisation. This is currently only exposed on SMP configurations.

Co-authored-by: Anna Lyons <anna@gh.st>

arm_hyp: Save and restore vtimer state on switches

Added support for reading and writing additional virtual timer
registers for vcpu hw read and write accesses. These include the
compare value register (CNTV_CVAL) and offset register (CNTV_OFF),
each represented as two 32 bit (high and low) registers on aarch32 and
as single 64 bit registers on aarch64.

Added support for explicitly saving and restoring the virtual
timer registers when the vcpu is enabled and disabled. This
ensures when the vcpu is switched in and out, the virtual timer
registers are restored to a state that is consistent to when
it was last run.

By default the CNTVOFF register will be updated by the kernel to
accumulate the time the VCPU is not running. From the guest this will
result in the VCNT register not increasing when the VCPU is suspended.
This behavior can be turned off by disabling the
KernelArmVtimerUpdateVOffset config option.

arm: New virtual PPI event fault type

This commit introduces a new fault type, seL4_Fault_VPPIEvent.

This change means the kernel can reserve PPI interrupts and virtualise
them via delivering the irq to the active vcpu through a
specific fault. This enables multiplexing PPI IRQs across multiple VCPUS
which requires correctly masking and unmasking the IRQ depending on
which VCPU is running.

A new VCPU invocation, seL4_ARM_VCPU_AckVPPI is also added for
acknowledging the handling of the IRQ. This takes an IRQ as a parameter
but will only accept IRQ numbers that are sent as VPPIEvent faults.

Co-authored-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
Co-authored-by: Kent McLeod <Kent.Mcleod@data61.csiro.au>

aarch64: Move tpidrro_el0 from vcpu to tcb context

This register is visible to software executing at EL0 but not writeable.
Storing it in the VCPU context required custom save/restore handling as
it had to be explicitly handled when switching from a VCPU thread to a
non-VCPU thread so that it didn't become a channel. It is possible to
now update this register via seL4_TCB_WriteRegisters for software
executing at EL0.

This also fixes a potential bug where if a vcpu-thread is switched for a
non-vcpu-thread and then switched to a different vcpu-thread the
original vcpu-thread's copy of this register will get set to 0.

mcs: timeout exceptions

- Add seL4_TCB_SetTimeoutEndpoint
- implement timeout exceptions

mcs: configurable scheduling context size

This allows users to define custom amounts of refills without
increasing the scheduling context size system wide.

also add libsel4 functions for refill size

mcs: associate scheduling context + ntfn

This commit allows scheduling contexts to be bound
to notification objects. When a passive server
receives a notification it will receive the scheduling
context from the notification. When the server
blocks the scheduling context is returned.

mcs: scheduling context donation over ipc

After this commit, threads blocked on an endpoint can recieve a
scheduling context from the thread that wakes the blocked thread.

mcs: add periodic scheduling

This commit adds periodic scheduling with sporadic servers.

mcs: Add a scheduling context object

This is the first part of the seL4 MCS. This commit:

* adds a scheduling context object. Threads without scheduling
context objects cannot be scheduled.
* replaces tcbTimeSlice with the scheduling context object
* adds seL4_SchedControl caps for each core
* adds seL4_SchedControl_Configure which allows users to configure
amount of ticks a scheduling context has, and set a core for the
scheduling context.
* adds seL4_SchedContext_Bind, Unbind and UnbindObject, which allows
a tcb to be bound to a scheduling context.

aarch64: add support for 40-bit PA

This commit adds support for using a 40-bit physical addresses in
aarch64-hyp mode.

40-bit PA support is implemented by using a 3-stage translation, with a
13 bit page upper directory as the vspace root. PageGlobalDirectories
are not used in this configuration.

To use 40-bit PAs, platforms should set KernelArmPASizeBits40 to ON.

Co-authored-by: Yanyan Shen <yanyan.shen@data61.csiro.au>
Co-authored-by: Chris Guikema <chris.guikema@dornerworks.com>

aarch64: abstract vspace_root in vspace code

On aarch64-hyp the virtual address translation structure can differ
depending on the physical address range. This commit prepares to support
more than a single physical address range by removing the assumption
that the top-level structure in a vspace is a PGD, replacing it with the
concept of a vspace_root.

Specifically:
- add and use macros to refer to vtable bitfield generator functions
- use the existing vspace_root_t type rather than pgde_t
- pull performASIDPoolInvocation into header
- add and use VSPACE_PTR rather than PGDE_PTR
- rename decodeARMVPageGlobalDirectoryInvocation to refer to VSpace
- update comments/error messages
- rename variables

RFC-3: Update user context for ARM with thread IDs

Switched appropriate naming conventions.
Was using the aarch64, have switched to aarch64 names.

TIPDRURW -> tpidr_el0
TPIDRURO -> tpidrro_el0
TPIDRPRW -> tpidr_el1

Switch TLS register on aarch32 from TPIDURO (tpidrro_el0) to tpidr_ro so
that it can be written to from user-land.

Thread ID registers tpidr_el0 have been added to the user context for
aarch32 and aarch64.

Only the thread ID that is writeable from EL0 is saved in the TCB and
saved/restored on context switch.

Thread IDs that are only changed within a VM (the read-only thread ID
for exception level 0 and the thread ID for exception level 1) are
stored in the VCPU and saved and stored as part of VM enable/disable.

Thread IDs that are only changed with VMs have been separated out into
hypervisor code.

libsel4: add seL4_VspaceBits

This constant represents the size of the root page table.

More standard constant name, moved ASID constants to arch generic files

Add seL4_UserTop and move kernelBase to the arch level

- seL4_UserTop is a new constant which represents the top of virtual
memory available to user level
- this commit also rationalises several constants (USER_TOP, kernelBase)
and moves them to the arch level, such that ports only need to define
seL4_UserTop.

armv8/hyp: Put CNTV_CTL before CNTV_TVAL

libsel4/armv8: Add seL4_VCPUReg for EL2

libsel4/armv8: Add VGICMaintenance_/VCPUFault_Msg

libsel4/armv8: Add seL4_ARM_VCPUBits&seL4_VCPUBits

Declare and check IPC buffer size

Adds a named constant of the IPC buffer size bits that can be used when checking the
size/alignment of an IPC buffer. This constant has a compile time assertion to ensure
it corresponds to the actual IPC buffer

libsel4: fix licenses

- some were incorrectly marked GPL (libsel4 is BSD)
- update NICTA --> DATA61 etc
- fix tags D61 --> DATA61
- update year to 2017

SELFOUR-879: expose index and entry constants

libsel4: Add seL4_FastMessageRegisters

This allows benchmarks and utility code to only set registers in the ipc
buffer as required.

s/D61/DATA61/ in license headers for consistency

aarch64: Add aarch64 libsel4 implementation