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00a9ba91 |
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12-May-2020 |
Kent McLeod <Kent.Mcleod@data61.csiro.au> |
aarch32: Move tpidruro from vcpu to tcb context This register is visible to software executing at PL0 but not writeable. Storing it in the VCPU context required custom save/restore handling as it had to be explicitly handled when switching from a VCPU thread to a non-VCPU thread so that it didn't become a channel. It is possible to now update this register via seL4_TCB_WriteRegisters for software executing at PL0. This also fixes a bug where if a vcpu-thread is switched for a non-vcpu-thread and then switched to a different vcpu-thread the original vcpu-thread's copy of this register will get set to 0. Signed-off-by: Kent McLeod <Kent.Mcleod@data61.csiro.au>
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512a0200 |
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19-Mar-2020 |
Qian Ge <qian.ge@data61.csiro.au> |
replacing all ifndef with pargma once All the kernel header files now use pargma once rather than the ifndef, as the pre-processed C files do not change while header files are protected with pargma once. This will also solve any naming issues caused by ifndef.
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79da0792 |
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01-Mar-2020 |
Gerwin Klein <gerwin.klein@data61.csiro.au> |
Convert license tags to SPDX identifiers This commit also converts our own copyright headers to directly use SPDX, but leaves all other copyright header intact, only adding the SPDX ident. As far as possible this commit also merges multiple Data61 copyright statements/headers into one for consistency.
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5646f774 |
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20-Mar-2019 |
Curtis Millar <curtis.millar@data61.csiro.au> |
RFC-3: Update user context for ARM with thread IDs Switched appropriate naming conventions. Was using the aarch64, have switched to aarch64 names. TIPDRURW -> tpidr_el0 TPIDRURO -> tpidrro_el0 TPIDRPRW -> tpidr_el1 Switch TLS register on aarch32 from TPIDURO (tpidrro_el0) to tpidr_ro so that it can be written to from user-land. Thread ID registers tpidr_el0 have been added to the user context for aarch32 and aarch64. Only the thread ID that is writeable from EL0 is saved in the TCB and saved/restored on context switch. Thread IDs that are only changed within a VM (the read-only thread ID for exception level 0 and the thread ID for exception level 1) are stored in the VCPU and saved and stored as part of VM enable/disable. Thread IDs that are only changed with VMs have been separated out into hypervisor code.
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07f94833 |
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18-Jun-2017 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
libsel4: fix licenses - some were incorrectly marked GPL (libsel4 is BSD) - update NICTA --> DATA61 etc - fix tags D61 --> DATA61 - update year to 2017
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6428e959 |
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12-Jan-2017 |
amrzar <azarrabi@nicta.com.au> |
aarch64: Add aarch64 libsel4 implementation
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b827ad37 |
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15-Jul-2016 |
Anna Lyons <Anna.Lyons@nicta.com.au> |
SELFOUR-413: refactor libsel4 fault API This is a *breaking API change* This commit: * makes seL4_Fault_tag_t common between the kernel and libsel4 * deprecates the existing functions from sel4/messages.h includes * introduces a new fault API in sel4/faults.h and * sel4/sel4_arch/faults.h * deprecates seL4_GetTag(), as the function did not work without the user calling seL4_SetTag() first (seL4_MessageInfo is passed in registers and not set in the IPC buffer) * removes previously deprecated functions (deprecated prior to 3.0.0) * updates the seL4 manual to reflect the changes
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289bf92b |
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05-Jan-2016 |
Anna Lyons <Anna.Lyons@nicta.com.au> |
SELFOUR-114: remove bootinfo.h duplication
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6523fe40 |
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21-Feb-2016 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
Correct previous merge
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cfcaf49c |
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31-Jan-2016 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
SELFOUR-399: object sizes and globals frame addr should come from the same source
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d1eb5a12 |
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01-Feb-2016 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
Correct previous merge
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1a1110a0 |
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14-Jan-2016 |
amrzar <azarrabi@nicta.com.au> |
Modify Kconfig and Makefile for aach32 as sel4_arch libsel4: updates to include aarch32 as sel4_arch
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