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e4b5099c |
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09-Sep-2020 |
Curtis Millar <curtis.millar@data61.csiro.au> |
risc-v: Implement benchmark timestamp Implements timestamp function used by benchmark logging utilities. Signed-off-by: Curtis Millar <curtis.millar@data61.csiro.au> Signed-off-by: Curtis Millar <curtis@curtism.me>
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512a0200 |
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19-Mar-2020 |
Qian Ge <qian.ge@data61.csiro.au> |
replacing all ifndef with pargma once All the kernel header files now use pargma once rather than the ifndef, as the pre-processed C files do not change while header files are protected with pargma once. This will also solve any naming issues caused by ifndef.
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79da0792 |
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01-Mar-2020 |
Gerwin Klein <gerwin.klein@data61.csiro.au> |
Convert license tags to SPDX identifiers This commit also converts our own copyright headers to directly use SPDX, but leaves all other copyright header intact, only adding the SPDX ident. As far as possible this commit also merges multiple Data61 copyright statements/headers into one for consistency.
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b5c56244 |
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07-Oct-2019 |
Simon Shields <simon.shields@data61.csiro.au> |
Create device untypeds at boot for all arches Currently on x86 device untypeds are generated by passing the entire address space minus any parts that are reserved by the kernel or that are "real" memory (e.g. kernel image, physical RAM). On ARM and RISC-V, device untypeds were generated at compile-time from a device tree. This patch moves ARM and RISC-V to use the same approach as x86, and moves the code from x86 into a common location that's shared between the three architectures. Co-Authored-By: Anna Lyons <anna@gh.st>
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375a98c8 |
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19-Jun-2019 |
Siwei Zhuang <siwei.zhuang@data61.csiro.au> |
CMake: Generate device headers from DTS for spike The DTS compilation was arm platforms only. Moving it to the top level config file, making it available to RISCV platforms. The generated files are almost identical with minor differences. A new argument(--arch) is added to the hardware_gen.py for the differences.
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83ba0847 |
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20-Feb-2018 |
Hesham Almatary <hesham.almatary@unsw.edu.au> |
[SELFOUR-1156] RISC-V Port Experimental release that supports both RV32 and RV64
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