SMMU: TLB coherency between MMU and SMMU

The kernel connects ASID used in MMU and context banks used in
SMMU, and conducts TLB invalidation on context banks if a page
entry is invalidated from MMU is also used in SMMU.

Signed-off-by: Oliver Scott <Oliver.Scott@data61.csiro.au>

aarch64: add missing vcpu cases

Adds missing vcpu cases for some aarch64-specific functions on
capabilities.

Signed-off-by: Nick Spinale <nick@nickspinale.com>

replacing all ifndef with pargma once

All the kernel header files now use pargma once rather than the ifndef,
as the pre-processed C files do not change while header files
are protected with pargma once. This will also solve any naming issues
caused by ifndef.

Convert license tags to SPDX identifiers

This commit also converts our own copyright headers to directly use
SPDX, but leaves all other copyright header intact, only adding the
SPDX ident. As far as possible this commit also merges multiple
Data61 copyright statements/headers into one for consistency.

aarch64: add support for 40-bit PA

This commit adds support for using a 40-bit physical addresses in
aarch64-hyp mode.

40-bit PA support is implemented by using a 3-stage translation, with a
13 bit page upper directory as the vspace root. PageGlobalDirectories
are not used in this configuration.

To use 40-bit PAs, platforms should set KernelArmPASizeBits40 to ON.

Co-authored-by: Yanyan Shen <yanyan.shen@data61.csiro.au>
Co-authored-by: Chris Guikema <chris.guikema@dornerworks.com>

aarch64: abstract vspace_root in vspace code

On aarch64-hyp the virtual address translation structure can differ
depending on the physical address range. This commit prepares to support
more than a single physical address range by removing the assumption
that the top-level structure in a vspace is a PGD, replacing it with the
concept of a vspace_root.

Specifically:
- add and use macros to refer to vtable bitfield generator functions
- use the existing vspace_root_t type rather than pgde_t
- pull performASIDPoolInvocation into header
- add and use VSPACE_PTR rather than PGDE_PTR
- rename decodeARMVPageGlobalDirectoryInvocation to refer to VSpace
- update comments/error messages
- rename variables

aarch64: adjustments to pass c-parser

This commit updates the aarch64 build to pass the c-parser.

- replace 0b constants with decimal
- remove empty array definition
- replace __uint128_t with uint64_t, and double the array size
- remove variable shadowing

No further verification guarantees are provided for aarch64 code.

More standard constant name, moved ASID constants to arch generic files

Remove symlinked libsel4 files from include dir

These files can be included normally using libsel4 include paths. This
removes situations where the same file is available under different
include paths due to symlinking into different directory structures.

style: consistently attach return type

Add attach-return-type to astyle

style: consistently align pointer with name

Run astyle with align-pointer=name

aarch64: Add pgde enum for tracking hyp hw_asids

aarch64 hyp mode only has support for 8 bit hardware ASIDs. We use the
same strategy used in aarch32 for hardware asids where we maintain a
pool of hwasids that seL4 ASIDs are allocated. The allocation is stored
in the last entry of top level paging structure. This commit
encapsulates this into the bitfield specification in the same way as
aarch32.

armv8: Add VCPU_PTR and VCPU_REF

armv8: Add VCPU_SIZE_BITS for EL2

armv8: Add tcbVCPU for EL2 arch_tcb

Fix licenses (the rest)

SELFOUR-879: expose index and entry constants

Pass tcb_t to sanitiseRegister instead of arch_tcb_t

s/D61/DATA61/ in license headers for consistency

aarch64: Initial implementation

aarch64: add preliminary folders and Makefiles