ar71xx: disable flow control to the built-in switch on AR934x

It apparently causes a regression on some devices if the ethernet cable
is plugged in while booting.

Signed-off-by: Felix Fietkau <nbd@nbd.name>

ar71xx: disable pdata->use_flow_control for QCA9558

Signed-off-by: Felix Fietkau <nbd@nbd.name>

ar71xx: rename ethernet pdata->builtin_switch to use_flow_control

Signed-off-by: Felix Fietkau <nbd@nbd.name>

ar71xx: enable flow control for ethernet MACs with built-in switch

Should fix LAN speed issues on some devices. This is an updated version
of the previously reverted commit with the same name.
It improves the check for MACs connected to a built-in switch

Signed-off-by: Felix Fietkau <nbd@nbd.name>

ar71xx: fix DDR write buffer flushing issues with 4.4

Signed-off-by: Felix Fietkau <nbd@nbd.name>

Revert "ar71xx: Clear bits in ath79_setup_qca955x_eth_cfg"

Not all mach-* files set all boards correctly in ETH_CFG. They depend on
some preset values by u-boot which were not previously modified by
ath79_setup_qca955x_eth_cfg. Avoiding to modify them in this function keeps
it backward compatible for these boards.

This reverts commit 119b8ab2c2eac237ec4e9c4d0ed53df22b5c6978.

Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@49072 3c298f89-4303-0410-b956-a3cf2f4a3e73

Revert "ar71xx: Allow to set the RXDV, RXD, TXD, TXE delays for QCA955x"

The default delays RXD 3. RDV 3, TXD 0, TXE 0 doesn't seem to work for some
boards. These boards depend on the preset values of u-boot which may
differ.

This reverts commit f2d4bb96b62512caa161dcc2867c91692fb16a38.

Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@49071 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: Allow to set the RXDV, RXD, TXD, TXE delays for QCA955x

Some u-boot versions for QCA955x change the delays based on the link speed
during boot. This usually breaks the support of other linkspeeds when
OpenWrt is booted. It also conflicts with the
at803x_platform_data::fixup_rgmii_tx_delay. OpenWrt has to set its own
values in QCA955X_GMAC_REG_ETH_CFG.

The default RGMII values from the Atheros u-boot are currently used to
preset the existing mach files. These may have to be adjusted for boards
using different values but which are not currently set them explicitely in
OpenWrt.

Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: Imre Kaloz <kaloz@openwrt.org>
Cc: Christian Beier <cb@shoutrlabs.com>
Cc: Chris R Blake <chrisrblake93@gmail.com>
Cc: Benjamin Berg <benjamin@sipsolutions.net>
Cc: Heiner Kallweit <hkallweit1@gmail.com>
Cc: Cezary Jackiewicz <cezary.jackiewicz@gmail.com>
Cc: Matthias Schiffer <mschiffer@universe-factory.net>
Cc: Dirk Neukirchen <dirkneukirchen@web.de>
Cc: Christian Mehlis <christian@m3hlis.de>
Cc: Luka Perkov <luka@openwrt.org>
Cc: Felix Fietkau <nbd@openwrt.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@49029 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: Clear bits in ath79_setup_qca955x_eth_cfg

Some u-boot versions for QCA955x set currently not cleared bits depending
on the used link speed. This breaks the rx/tx under OpenWrt. The mach-*.c
file is responsible to select the correct configuration bits and thus the
ath79_setup_qca955x_eth_cfg has to clear the unset.

Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@49028 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: fix qca956x ethernet initialization

Complete internal switch initialization for QCA956X.
Set default mdio device if the interface mode of GE0 is not SGMII (fix ticket #21520).

Signed-off-by: Weijie Gao <hackpascal@gmail.com>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@48937 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: fix MDIO bus probe on QCA956x

Signed-off-by: Felix Fietkau <nbd@openwrt.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@48651 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: fold patch 622-MIPS-ath79-add-support-for-QCA956x-ethernet.patch into files/

Signed-off-by: Felix Fietkau <nbd@openwrt.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@48650 3c298f89-4303-0410-b956-a3cf2f4a3e73

ath79: dev-eth: fix QCA9561 set phy interface mode and mask

QCA9563 and QCA9561 are two series of Qualcomm SoC Dragonfly. The only different
is QCA9563 w/o internal switch. It has one GMAC with SGMII interface. But they
have the same device ID(0x1150). So they share the same codes.

Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@46971 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: rework patch for qca953x/956x

Patch cherry-picked from the following location:
https://www.codeaurora.org/cgit/quic/qsdk/oss/system/openwrt/commit/?h=release/coconut_ioe4531_2.0&id=5c357bf6c763e4140dddcc9a3bc5f005525a9c0e

Changelist,
- add more register defines
- add EHCI support
- fix GPIO pin count to 18
- fix chained irq disabled
- fix GMAC0/GMAC1 initial
- fix WMAC irq number to 47
- merge the changes of dev-eth.c from the patch to file.

Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org>
Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@46207 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: add a helper function to set RXDV/RXD of ETH_CFG on AR934x

The ETH_RXDV_DELAY (17:16) and ETH_RXD_DELAY (15:14) are currently not cleared
by the function ath79_setup_ar934x_eth_cfg. Clearing these in the
ath79_setup_ar934x_eth_cfg may cause problems on some hardware because they
rely on the preset value by the bootloader.

Instead another function is introduced which also works on ETH_CFG on AR934x.
It can be used to safely clear and set ETH_RXDV_DELAY and ETH_RXD_DELAY on
machines which require special settings.

Signed-off-by: Sven Eckelmann <sven@open-mesh.com>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@45523 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: dev-eth: replace mdelay calls

Similar to patch 2. Replace further mdelay calls.

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@43540 3c298f89-4303-0410-b956-a3cf2f4a3e73

ath79: dev-eth: Don't advertise 1gbit in link code word on ar9331

While the AR9331 has a gigabit MAC towards the internal switch, the
integrated PHYs however are only 100-base-tx capable. The existing code
however advertieses gigabit capability in the link status word. If you
attach such a PHY to a gigabit capable switch on the remote end, with
some probability it attempts to negotiate gigabit and fails, falling
baco to the AR9331 assuming a 10mbit half-duplex link. This has been
observed quite frequently with the Carambola2 and gigabit capable
switches.

In ath79_register_eth(), "pdata->has_gbit = 1;" is set unconditionally
for both AR9331 ethernet ports. This is most likely wrong. Despite the
two MAC IP cores being gigabit MACs, the MAC for eth1 is connected to a
100base-T PHY via MII. The has_gbit attribute is used in the ethernet
driver to determine the supported link modes.

So either pdata->has_gbit is not set to 1 anymore, or the ethernet
driver needs to be modified to determine the advertised link code word
on another criteria than pdata->has_gbit. This patch implements the
former solution.

Signed-off-by: Harald Welte <laforge@gnumonks.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@42432 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: add a helper function for setting up ETH_CFG register on QCA955x

Signed-off-by: Jon Suphammer <jon@suphammer.net>
Patchwork: http://patchwork.openwrt.org/patch/5839/
[juhosg: fix coding style]
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@41623 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: add support for QCA953x SoC

I don't have access to the specs, so I'm not sure about every detail, but I
haven't seen any problems with my test system, a TL-WR841N v9. It looks pretty
much like a QCA955x without PCI, a little twist in the clock calculation and
a AR9331-compatible switch.

Features not yet supported:

* EHCI (my test system doesn't have USB)
* ? (I have no idea if the QCA953x has any other features I don't know about
that aren't used by the TL-WR841N v9)

Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@40399 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: fix max frame length of the QCA955x SoCs

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@39161 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: don't set builtin_switch flag for QCA9558

It makes no sense, the SoC has no built-in switch.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@39160 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: allow to use large ethernet frames on AR934x SoCs

The hardware supports large ethernet frames. Override
the maximum frame length and packet lenght mask in the
platform data to allow to use large MTU on the ethernet
interfaces.

Limit the feature to AR934x SoCs for now. It should work
on some other SoCs as well, but those has not been tested
yet.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@39149 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: ag71xx: get max_frame_len and desc_pktlen_mask from platform data

This will allow to use SoC specific values for both.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@39145 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: make ag71xx_mdio_platform_data visible

This enables us to modify the ag71xx_mdio_platform_data from within the
board support files.

Signed-off-by: Felix Kaechele <heffer@fedoraproject.org>
Patchwork: http://patchwork.openwrt.org/patch/4613/
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@39126 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: rename ath79_parse_mac_addr to ath79_parse_ascii_mac

Rename the function and extend it in order to make it
usable from board setup code.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@38085 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: use backported QCA955x patches

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@35878 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: fix ethernet device registration for the QCA9556 SoC

Based on http://patchwork.openwrt.org/patch/3162/

Signed-off-by: Embedded Wireless GmbH <info at embeddedwireless.de>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@35394 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: fix ethernet device registration for QCA9558

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34853 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: fixup allowed PHY interface types for QCA9558

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34851 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: don't assign any MII bus device on QCA9558 by default

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34850 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: add a helper function for setting up ETH_CFG register on AR934x

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33817 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: avoid possible NULL pointer dereference in ath79_init_{,local}_mac

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33575 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: use dynamic clock dividers on the 2nd MDIO of AR934x

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33343 3c298f89-4303-0410-b956-a3cf2f4a3e73

Revert "ar71xx: only allow RGMII mode on the 2nd ethernet MAC of the AR7240"

That was based on assumptions.

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33310 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: only allow RGMII mode on the 2nd ethernet MAC of the AR7240

Signed-off-by: Daniel Golle <dgolle@allnet.de>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33280 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: add initial support for the QCA955X SoCs

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32606 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: add a helper function for setting up PHY4 swapping on ar933x

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32092 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: fix MII clock settings for various chips, improves ethernet stability on AR934x

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31925 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: allow to disable link polling on unused PHYs

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31533 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: add AR934x specific interface speed setup for ge0

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31017 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: reset the switch on AR934x before ethernet device registration

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@30922 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: use a dummy callback for interfaces with fixed speed

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@30913 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: merge ar934x_bo_ddr_flush patch

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@30912 3c298f89-4303-0410-b956-a3cf2f4a3e73

ar71xx: merge files-3.2 to files

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@30405 3c298f89-4303-0410-b956-a3cf2f4a3e73