remove unneeded includes; ok miod@

remove prototypes with no matching function
ok mpi@

Make ifq and ifiq interface MP safe.

Rename ifq_set_maxlen() to ifq_init_maxlen(). This function neither
uses WRITE_ONCE() nor a mutex and is called before the ifq mutex
is initialized. The new name expresses that it should be used only
during interface attach when there is no concurrency.

Protect ifq_len(), ifq_empty(), ifiq_len(), and ifiq_empty() with
READ_ONCE(). They can be used without lock as they only read a
single integer.

OK dlg@

Atlantic 2 hardware has a different layout for the TPS_DATA_TCT registers
and uses different buffer sizes. Fixes an issue where the card would
stop transmitting packets under load on the M2 Pro Mac mini.

ok jmatthew@

avoid c99 for-scope variable decl
ok jmatthew@

Replace a bunch of (1 << 31) with (1U << 31)

Remove bogus newline in printf.

ok jmatthew@

The built-in 10G Ethernet on Apple arm64 hardware does not have a MAC
address programmed into the hardware. Get it from the device tree instead.

ok dlg@, jmatthew@

Add initial support for Atlantic 2 hardware. Atlantic 2 has
much more complicated rx processing, and here we're doing the
bare minimum to get packets moving. RSS is not implemented yet,
vlans and multicast (among others) probably don't work yet either.

tested by kettenis@ on an M2 Mac Mini, and by me on an AQC113
card provided by Brad
ok dlg@

Adjust some printfs in the attach code path to make more sense,
and include the mac address of the interface on the attach line.

ok dlg@

Prepare for adding Atlantic 2 support by renaming functions and defines
specific to Atlantic 1, shuffling some of the setup code, and adding
get_mac_addr to the firmware ops struct.

ok dlg@

As with if_em.c r1.350, and for the same reasons (arm64 systems with non
cache coherent PCIe), map the rx and tx rings coherent.

tested by kevlo@ on rockpro64
ok dlg@

constify struct cfattach

Add dmamap syncs for rings and mbufs, fixing occasional errors seen
on a rockpro64, where dma is less coherent than on typical amd64 systems.

with and ok dlg@

If we've created multiple queues, set up an RSS key and indirection table
to distribute received packets across the queues.

ok dlg@

If enough MSI-X vectors are available, set up multiple tx and rx queues.
In multi-vector mode, the MSI-X vector number is the same as the irq number
on the nic, so use vector/irq 0 for link interrupts, then assign one to
each pair of rx and tx queues. We don't configure RSS yet, so packets
will only be received on the first queue, but they can be transmitted on
any queue.

ok dlg@

Expand tx dma maps to allow packets up to the MTU limit to be transmitted.
Don't clear TPB_TX_BUF_EN when taking the interface down, as somehow that
causes transmission to fail when the interface comes up again if any large
packets had been sent.

Handle packets received into multiple rx buffers using the same approach as
ixl(4), with the addition that a receive error can be signaled on any of
the buffers rather than just the last one. Set the low water mark on the
rx ring so there are always enough buffers to receive the largest packet
supported by the interface, and fix the calculation of the data pointer
in rx buffers so there's actually MCLBYTES space available.

ok dlg@

Enable interrupt moderation, targeting around 20k interrupts per second.
There are separate timers for rx and tx interrupts, so we can use longer
timeouts for tx since that doesn't affect packet processing latency.

ok dlg@

Enable checksum offloads. The nic does all the work here, so we don't
need to calculate header offsets for it.

ok dlg@

Enable vlan promisc and header stripping, and use vlan rx/tx offloads.
The vlan tx information takes up an extra slot on the tx ring, so this
affects the point at which we stop putting packets on the ring too.

ok dlg@

Transmit segmented packets using multiple tx ring slots rather than
defragging them first.

ok dlg@

Fix receive filter handling. Update the unicast mac address in the filter
when bringing the interface up, so it's possible to change it with
ifconfig. Rearrange multicast handling so IFF_ALLMULTI is set correctly
and multicast ranges don't trigger promisc mode. Perhaps most importantly,
set RPF_MCAST_FILTER_EN to 0 when we don't want all multicast traffic -
we use mac address filters to receive specific multicast groups, and the
multicast filter is programmed to accept all multicast traffic.

based on a diff from Brad
ok dlg@

Invalidate the nic's rx descriptor cache when taking the interface up
or down, and turn off the global tx and rx enables when going down.
Without this, the nic can write to mbufs that were taken off the ring
when the interface was taken down, triggering mbuf cluster pool use
after free checks.

ok dlg@

Handle rxrinfo ioctl.

ok dlg@

No need to enable bus mastering, it's already done for us.

from Brad

wire up bpf correctly

ok dlg@ deraadt@

pci_mapreg_map() will assign an address to the BAR if it doesn't have one
already, so we shouldn't refuse to attach in that case.

noticed by kevlo@ on arm64
ok dlg@ deraadt@

aq(4) driver for Aquantia 1/2.5/5/10Gb/s PCIe ethernet adapters

Adds support for Aquantia AQC1xx family of PCIe ethernet adapters. This
driver supports 1Gbps through 10Gbps modes of operation based on the
hardware and media/switch capabilities.

The initial code was ported from NetBSD, with jmatthew@ finishing up
the Tx/Rx ring support and interrupt handler routine.

The driver only supports devices using firmware V2.

This diff enables aq(4) on riscv64 and amd64, the only platforms where
I have tested the driver, but it likely works on other architectures
as well.

remove prototypes with no matching function
ok mpi@

Make ifq and ifiq interface MP safe.

Rename ifq_set_maxlen() to ifq_init_maxlen(). This function neither
uses WRITE_ONCE() nor a mutex and is called before the ifq mutex
is initialized. The new name expresses that it should be used only
during interface attach when there is no concurrency.

Protect ifq_len(), ifq_empty(), ifiq_len(), and ifiq_empty() with
READ_ONCE(). They can be used without lock as they only read a
single integer.

OK dlg@

Atlantic 2 hardware has a different layout for the TPS_DATA_TCT registers
and uses different buffer sizes. Fixes an issue where the card would
stop transmitting packets under load on the M2 Pro Mac mini.

ok jmatthew@

avoid c99 for-scope variable decl
ok jmatthew@

Replace a bunch of (1 << 31) with (1U << 31)

Remove bogus newline in printf.

ok jmatthew@

The built-in 10G Ethernet on Apple arm64 hardware does not have a MAC
address programmed into the hardware. Get it from the device tree instead.

ok dlg@, jmatthew@

Add initial support for Atlantic 2 hardware. Atlantic 2 has
much more complicated rx processing, and here we're doing the
bare minimum to get packets moving. RSS is not implemented yet,
vlans and multicast (among others) probably don't work yet either.

tested by kettenis@ on an M2 Mac Mini, and by me on an AQC113
card provided by Brad
ok dlg@

Adjust some printfs in the attach code path to make more sense,
and include the mac address of the interface on the attach line.

ok dlg@

Prepare for adding Atlantic 2 support by renaming functions and defines
specific to Atlantic 1, shuffling some of the setup code, and adding
get_mac_addr to the firmware ops struct.

ok dlg@

As with if_em.c r1.350, and for the same reasons (arm64 systems with non
cache coherent PCIe), map the rx and tx rings coherent.

tested by kevlo@ on rockpro64
ok dlg@

constify struct cfattach

Add dmamap syncs for rings and mbufs, fixing occasional errors seen
on a rockpro64, where dma is less coherent than on typical amd64 systems.

with and ok dlg@

If we've created multiple queues, set up an RSS key and indirection table
to distribute received packets across the queues.

ok dlg@

If enough MSI-X vectors are available, set up multiple tx and rx queues.
In multi-vector mode, the MSI-X vector number is the same as the irq number
on the nic, so use vector/irq 0 for link interrupts, then assign one to
each pair of rx and tx queues. We don't configure RSS yet, so packets
will only be received on the first queue, but they can be transmitted on
any queue.

ok dlg@

Expand tx dma maps to allow packets up to the MTU limit to be transmitted.
Don't clear TPB_TX_BUF_EN when taking the interface down, as somehow that
causes transmission to fail when the interface comes up again if any large
packets had been sent.

Handle packets received into multiple rx buffers using the same approach as
ixl(4), with the addition that a receive error can be signaled on any of
the buffers rather than just the last one. Set the low water mark on the
rx ring so there are always enough buffers to receive the largest packet
supported by the interface, and fix the calculation of the data pointer
in rx buffers so there's actually MCLBYTES space available.

ok dlg@

Enable interrupt moderation, targeting around 20k interrupts per second.
There are separate timers for rx and tx interrupts, so we can use longer
timeouts for tx since that doesn't affect packet processing latency.

ok dlg@

Enable checksum offloads. The nic does all the work here, so we don't
need to calculate header offsets for it.

ok dlg@

Enable vlan promisc and header stripping, and use vlan rx/tx offloads.
The vlan tx information takes up an extra slot on the tx ring, so this
affects the point at which we stop putting packets on the ring too.

ok dlg@

Transmit segmented packets using multiple tx ring slots rather than
defragging them first.

ok dlg@

Fix receive filter handling. Update the unicast mac address in the filter
when bringing the interface up, so it's possible to change it with
ifconfig. Rearrange multicast handling so IFF_ALLMULTI is set correctly
and multicast ranges don't trigger promisc mode. Perhaps most importantly,
set RPF_MCAST_FILTER_EN to 0 when we don't want all multicast traffic -
we use mac address filters to receive specific multicast groups, and the
multicast filter is programmed to accept all multicast traffic.

based on a diff from Brad
ok dlg@

Invalidate the nic's rx descriptor cache when taking the interface up
or down, and turn off the global tx and rx enables when going down.
Without this, the nic can write to mbufs that were taken off the ring
when the interface was taken down, triggering mbuf cluster pool use
after free checks.

ok dlg@

Handle rxrinfo ioctl.

ok dlg@

No need to enable bus mastering, it's already done for us.

from Brad

wire up bpf correctly

ok dlg@ deraadt@

pci_mapreg_map() will assign an address to the BAR if it doesn't have one
already, so we shouldn't refuse to attach in that case.

noticed by kevlo@ on arm64
ok dlg@ deraadt@

aq(4) driver for Aquantia 1/2.5/5/10Gb/s PCIe ethernet adapters

Adds support for Aquantia AQC1xx family of PCIe ethernet adapters. This
driver supports 1Gbps through 10Gbps modes of operation based on the
hardware and media/switch capabilities.

The initial code was ported from NetBSD, with jmatthew@ finishing up
the Tx/Rx ring support and interrupt handler routine.

The driver only supports devices using firmware V2.

This diff enables aq(4) on riscv64 and amd64, the only platforms where
I have tested the driver, but it likely works on other architectures
as well.

Make ifq and ifiq interface MP safe.

Rename ifq_set_maxlen() to ifq_init_maxlen(). This function neither
uses WRITE_ONCE() nor a mutex and is called before the ifq mutex
is initialized. The new name expresses that it should be used only
during interface attach when there is no concurrency.

Protect ifq_len(), ifq_empty(), ifiq_len(), and ifiq_empty() with
READ_ONCE(). They can be used without lock as they only read a
single integer.

OK dlg@

Atlantic 2 hardware has a different layout for the TPS_DATA_TCT registers
and uses different buffer sizes. Fixes an issue where the card would
stop transmitting packets under load on the M2 Pro Mac mini.

ok jmatthew@

avoid c99 for-scope variable decl
ok jmatthew@

Replace a bunch of (1 << 31) with (1U << 31)

Remove bogus newline in printf.

ok jmatthew@

The built-in 10G Ethernet on Apple arm64 hardware does not have a MAC
address programmed into the hardware. Get it from the device tree instead.

ok dlg@, jmatthew@

Add initial support for Atlantic 2 hardware. Atlantic 2 has
much more complicated rx processing, and here we're doing the
bare minimum to get packets moving. RSS is not implemented yet,
vlans and multicast (among others) probably don't work yet either.

tested by kettenis@ on an M2 Mac Mini, and by me on an AQC113
card provided by Brad
ok dlg@

Adjust some printfs in the attach code path to make more sense,
and include the mac address of the interface on the attach line.

ok dlg@

Prepare for adding Atlantic 2 support by renaming functions and defines
specific to Atlantic 1, shuffling some of the setup code, and adding
get_mac_addr to the firmware ops struct.

ok dlg@

As with if_em.c r1.350, and for the same reasons (arm64 systems with non
cache coherent PCIe), map the rx and tx rings coherent.

tested by kevlo@ on rockpro64
ok dlg@

constify struct cfattach

Add dmamap syncs for rings and mbufs, fixing occasional errors seen
on a rockpro64, where dma is less coherent than on typical amd64 systems.

with and ok dlg@

If we've created multiple queues, set up an RSS key and indirection table
to distribute received packets across the queues.

ok dlg@

If enough MSI-X vectors are available, set up multiple tx and rx queues.
In multi-vector mode, the MSI-X vector number is the same as the irq number
on the nic, so use vector/irq 0 for link interrupts, then assign one to
each pair of rx and tx queues. We don't configure RSS yet, so packets
will only be received on the first queue, but they can be transmitted on
any queue.

ok dlg@

Expand tx dma maps to allow packets up to the MTU limit to be transmitted.
Don't clear TPB_TX_BUF_EN when taking the interface down, as somehow that
causes transmission to fail when the interface comes up again if any large
packets had been sent.

Handle packets received into multiple rx buffers using the same approach as
ixl(4), with the addition that a receive error can be signaled on any of
the buffers rather than just the last one. Set the low water mark on the
rx ring so there are always enough buffers to receive the largest packet
supported by the interface, and fix the calculation of the data pointer
in rx buffers so there's actually MCLBYTES space available.

ok dlg@

Enable interrupt moderation, targeting around 20k interrupts per second.
There are separate timers for rx and tx interrupts, so we can use longer
timeouts for tx since that doesn't affect packet processing latency.

ok dlg@

Enable checksum offloads. The nic does all the work here, so we don't
need to calculate header offsets for it.

ok dlg@

Enable vlan promisc and header stripping, and use vlan rx/tx offloads.
The vlan tx information takes up an extra slot on the tx ring, so this
affects the point at which we stop putting packets on the ring too.

ok dlg@

Transmit segmented packets using multiple tx ring slots rather than
defragging them first.

ok dlg@

Fix receive filter handling. Update the unicast mac address in the filter
when bringing the interface up, so it's possible to change it with
ifconfig. Rearrange multicast handling so IFF_ALLMULTI is set correctly
and multicast ranges don't trigger promisc mode. Perhaps most importantly,
set RPF_MCAST_FILTER_EN to 0 when we don't want all multicast traffic -
we use mac address filters to receive specific multicast groups, and the
multicast filter is programmed to accept all multicast traffic.

based on a diff from Brad
ok dlg@

Invalidate the nic's rx descriptor cache when taking the interface up
or down, and turn off the global tx and rx enables when going down.
Without this, the nic can write to mbufs that were taken off the ring
when the interface was taken down, triggering mbuf cluster pool use
after free checks.

ok dlg@

Handle rxrinfo ioctl.

ok dlg@

No need to enable bus mastering, it's already done for us.

from Brad

wire up bpf correctly

ok dlg@ deraadt@

pci_mapreg_map() will assign an address to the BAR if it doesn't have one
already, so we shouldn't refuse to attach in that case.

noticed by kevlo@ on arm64
ok dlg@ deraadt@

aq(4) driver for Aquantia 1/2.5/5/10Gb/s PCIe ethernet adapters

Adds support for Aquantia AQC1xx family of PCIe ethernet adapters. This
driver supports 1Gbps through 10Gbps modes of operation based on the
hardware and media/switch capabilities.

The initial code was ported from NetBSD, with jmatthew@ finishing up
the Tx/Rx ring support and interrupt handler routine.

The driver only supports devices using firmware V2.

This diff enables aq(4) on riscv64 and amd64, the only platforms where
I have tested the driver, but it likely works on other architectures
as well.

Atlantic 2 hardware has a different layout for the TPS_DATA_TCT registers
and uses different buffer sizes. Fixes an issue where the card would
stop transmitting packets under load on the M2 Pro Mac mini.

ok jmatthew@

avoid c99 for-scope variable decl
ok jmatthew@

Replace a bunch of (1 << 31) with (1U << 31)

Remove bogus newline in printf.

ok jmatthew@

The built-in 10G Ethernet on Apple arm64 hardware does not have a MAC
address programmed into the hardware. Get it from the device tree instead.

ok dlg@, jmatthew@

Add initial support for Atlantic 2 hardware. Atlantic 2 has
much more complicated rx processing, and here we're doing the
bare minimum to get packets moving. RSS is not implemented yet,
vlans and multicast (among others) probably don't work yet either.

tested by kettenis@ on an M2 Mac Mini, and by me on an AQC113
card provided by Brad
ok dlg@

Adjust some printfs in the attach code path to make more sense,
and include the mac address of the interface on the attach line.

ok dlg@

Prepare for adding Atlantic 2 support by renaming functions and defines
specific to Atlantic 1, shuffling some of the setup code, and adding
get_mac_addr to the firmware ops struct.

ok dlg@

As with if_em.c r1.350, and for the same reasons (arm64 systems with non
cache coherent PCIe), map the rx and tx rings coherent.

tested by kevlo@ on rockpro64
ok dlg@

constify struct cfattach

Add dmamap syncs for rings and mbufs, fixing occasional errors seen
on a rockpro64, where dma is less coherent than on typical amd64 systems.

with and ok dlg@

If we've created multiple queues, set up an RSS key and indirection table
to distribute received packets across the queues.

ok dlg@

If enough MSI-X vectors are available, set up multiple tx and rx queues.
In multi-vector mode, the MSI-X vector number is the same as the irq number
on the nic, so use vector/irq 0 for link interrupts, then assign one to
each pair of rx and tx queues. We don't configure RSS yet, so packets
will only be received on the first queue, but they can be transmitted on
any queue.

ok dlg@

Expand tx dma maps to allow packets up to the MTU limit to be transmitted.
Don't clear TPB_TX_BUF_EN when taking the interface down, as somehow that
causes transmission to fail when the interface comes up again if any large
packets had been sent.

Handle packets received into multiple rx buffers using the same approach as
ixl(4), with the addition that a receive error can be signaled on any of
the buffers rather than just the last one. Set the low water mark on the
rx ring so there are always enough buffers to receive the largest packet
supported by the interface, and fix the calculation of the data pointer
in rx buffers so there's actually MCLBYTES space available.

ok dlg@

Enable interrupt moderation, targeting around 20k interrupts per second.
There are separate timers for rx and tx interrupts, so we can use longer
timeouts for tx since that doesn't affect packet processing latency.

ok dlg@

Enable checksum offloads. The nic does all the work here, so we don't
need to calculate header offsets for it.

ok dlg@

Enable vlan promisc and header stripping, and use vlan rx/tx offloads.
The vlan tx information takes up an extra slot on the tx ring, so this
affects the point at which we stop putting packets on the ring too.

ok dlg@

Transmit segmented packets using multiple tx ring slots rather than
defragging them first.

ok dlg@

Fix receive filter handling. Update the unicast mac address in the filter
when bringing the interface up, so it's possible to change it with
ifconfig. Rearrange multicast handling so IFF_ALLMULTI is set correctly
and multicast ranges don't trigger promisc mode. Perhaps most importantly,
set RPF_MCAST_FILTER_EN to 0 when we don't want all multicast traffic -
we use mac address filters to receive specific multicast groups, and the
multicast filter is programmed to accept all multicast traffic.

based on a diff from Brad
ok dlg@

Invalidate the nic's rx descriptor cache when taking the interface up
or down, and turn off the global tx and rx enables when going down.
Without this, the nic can write to mbufs that were taken off the ring
when the interface was taken down, triggering mbuf cluster pool use
after free checks.

ok dlg@

Handle rxrinfo ioctl.

ok dlg@

No need to enable bus mastering, it's already done for us.

from Brad

wire up bpf correctly

ok dlg@ deraadt@

pci_mapreg_map() will assign an address to the BAR if it doesn't have one
already, so we shouldn't refuse to attach in that case.

noticed by kevlo@ on arm64
ok dlg@ deraadt@

aq(4) driver for Aquantia 1/2.5/5/10Gb/s PCIe ethernet adapters

Adds support for Aquantia AQC1xx family of PCIe ethernet adapters. This
driver supports 1Gbps through 10Gbps modes of operation based on the
hardware and media/switch capabilities.

The initial code was ported from NetBSD, with jmatthew@ finishing up
the Tx/Rx ring support and interrupt handler routine.

The driver only supports devices using firmware V2.

This diff enables aq(4) on riscv64 and amd64, the only platforms where
I have tested the driver, but it likely works on other architectures
as well.

avoid c99 for-scope variable decl
ok jmatthew@

Replace a bunch of (1 << 31) with (1U << 31)

Remove bogus newline in printf.

ok jmatthew@

The built-in 10G Ethernet on Apple arm64 hardware does not have a MAC
address programmed into the hardware. Get it from the device tree instead.

ok dlg@, jmatthew@

Add initial support for Atlantic 2 hardware. Atlantic 2 has
much more complicated rx processing, and here we're doing the
bare minimum to get packets moving. RSS is not implemented yet,
vlans and multicast (among others) probably don't work yet either.

tested by kettenis@ on an M2 Mac Mini, and by me on an AQC113
card provided by Brad
ok dlg@

Adjust some printfs in the attach code path to make more sense,
and include the mac address of the interface on the attach line.

ok dlg@

Prepare for adding Atlantic 2 support by renaming functions and defines
specific to Atlantic 1, shuffling some of the setup code, and adding
get_mac_addr to the firmware ops struct.

ok dlg@

As with if_em.c r1.350, and for the same reasons (arm64 systems with non
cache coherent PCIe), map the rx and tx rings coherent.

tested by kevlo@ on rockpro64
ok dlg@

constify struct cfattach

Add dmamap syncs for rings and mbufs, fixing occasional errors seen
on a rockpro64, where dma is less coherent than on typical amd64 systems.

with and ok dlg@

If we've created multiple queues, set up an RSS key and indirection table
to distribute received packets across the queues.

ok dlg@

If enough MSI-X vectors are available, set up multiple tx and rx queues.
In multi-vector mode, the MSI-X vector number is the same as the irq number
on the nic, so use vector/irq 0 for link interrupts, then assign one to
each pair of rx and tx queues. We don't configure RSS yet, so packets
will only be received on the first queue, but they can be transmitted on
any queue.

ok dlg@

Expand tx dma maps to allow packets up to the MTU limit to be transmitted.
Don't clear TPB_TX_BUF_EN when taking the interface down, as somehow that
causes transmission to fail when the interface comes up again if any large
packets had been sent.

Handle packets received into multiple rx buffers using the same approach as
ixl(4), with the addition that a receive error can be signaled on any of
the buffers rather than just the last one. Set the low water mark on the
rx ring so there are always enough buffers to receive the largest packet
supported by the interface, and fix the calculation of the data pointer
in rx buffers so there's actually MCLBYTES space available.

ok dlg@

Enable interrupt moderation, targeting around 20k interrupts per second.
There are separate timers for rx and tx interrupts, so we can use longer
timeouts for tx since that doesn't affect packet processing latency.

ok dlg@

Enable checksum offloads. The nic does all the work here, so we don't
need to calculate header offsets for it.

ok dlg@

Enable vlan promisc and header stripping, and use vlan rx/tx offloads.
The vlan tx information takes up an extra slot on the tx ring, so this
affects the point at which we stop putting packets on the ring too.

ok dlg@

Transmit segmented packets using multiple tx ring slots rather than
defragging them first.

ok dlg@

Fix receive filter handling. Update the unicast mac address in the filter
when bringing the interface up, so it's possible to change it with
ifconfig. Rearrange multicast handling so IFF_ALLMULTI is set correctly
and multicast ranges don't trigger promisc mode. Perhaps most importantly,
set RPF_MCAST_FILTER_EN to 0 when we don't want all multicast traffic -
we use mac address filters to receive specific multicast groups, and the
multicast filter is programmed to accept all multicast traffic.

based on a diff from Brad
ok dlg@

Invalidate the nic's rx descriptor cache when taking the interface up
or down, and turn off the global tx and rx enables when going down.
Without this, the nic can write to mbufs that were taken off the ring
when the interface was taken down, triggering mbuf cluster pool use
after free checks.

ok dlg@

Handle rxrinfo ioctl.

ok dlg@

No need to enable bus mastering, it's already done for us.

from Brad

wire up bpf correctly

ok dlg@ deraadt@

pci_mapreg_map() will assign an address to the BAR if it doesn't have one
already, so we shouldn't refuse to attach in that case.

noticed by kevlo@ on arm64
ok dlg@ deraadt@

aq(4) driver for Aquantia 1/2.5/5/10Gb/s PCIe ethernet adapters

Adds support for Aquantia AQC1xx family of PCIe ethernet adapters. This
driver supports 1Gbps through 10Gbps modes of operation based on the
hardware and media/switch capabilities.

The initial code was ported from NetBSD, with jmatthew@ finishing up
the Tx/Rx ring support and interrupt handler routine.

The driver only supports devices using firmware V2.

This diff enables aq(4) on riscv64 and amd64, the only platforms where
I have tested the driver, but it likely works on other architectures
as well.

Replace a bunch of (1 << 31) with (1U << 31)

Remove bogus newline in printf.

ok jmatthew@

The built-in 10G Ethernet on Apple arm64 hardware does not have a MAC
address programmed into the hardware. Get it from the device tree instead.

ok dlg@, jmatthew@

Add initial support for Atlantic 2 hardware. Atlantic 2 has
much more complicated rx processing, and here we're doing the
bare minimum to get packets moving. RSS is not implemented yet,
vlans and multicast (among others) probably don't work yet either.

tested by kettenis@ on an M2 Mac Mini, and by me on an AQC113
card provided by Brad
ok dlg@

Adjust some printfs in the attach code path to make more sense,
and include the mac address of the interface on the attach line.

ok dlg@

Prepare for adding Atlantic 2 support by renaming functions and defines
specific to Atlantic 1, shuffling some of the setup code, and adding
get_mac_addr to the firmware ops struct.

ok dlg@

As with if_em.c r1.350, and for the same reasons (arm64 systems with non
cache coherent PCIe), map the rx and tx rings coherent.

tested by kevlo@ on rockpro64
ok dlg@

constify struct cfattach

Add dmamap syncs for rings and mbufs, fixing occasional errors seen
on a rockpro64, where dma is less coherent than on typical amd64 systems.

with and ok dlg@

If we've created multiple queues, set up an RSS key and indirection table
to distribute received packets across the queues.

ok dlg@

If enough MSI-X vectors are available, set up multiple tx and rx queues.
In multi-vector mode, the MSI-X vector number is the same as the irq number
on the nic, so use vector/irq 0 for link interrupts, then assign one to
each pair of rx and tx queues. We don't configure RSS yet, so packets
will only be received on the first queue, but they can be transmitted on
any queue.

ok dlg@

Expand tx dma maps to allow packets up to the MTU limit to be transmitted.
Don't clear TPB_TX_BUF_EN when taking the interface down, as somehow that
causes transmission to fail when the interface comes up again if any large
packets had been sent.

Handle packets received into multiple rx buffers using the same approach as
ixl(4), with the addition that a receive error can be signaled on any of
the buffers rather than just the last one. Set the low water mark on the
rx ring so there are always enough buffers to receive the largest packet
supported by the interface, and fix the calculation of the data pointer
in rx buffers so there's actually MCLBYTES space available.

ok dlg@

Enable interrupt moderation, targeting around 20k interrupts per second.
There are separate timers for rx and tx interrupts, so we can use longer
timeouts for tx since that doesn't affect packet processing latency.

ok dlg@

Enable checksum offloads. The nic does all the work here, so we don't
need to calculate header offsets for it.

ok dlg@

Enable vlan promisc and header stripping, and use vlan rx/tx offloads.
The vlan tx information takes up an extra slot on the tx ring, so this
affects the point at which we stop putting packets on the ring too.

ok dlg@

Transmit segmented packets using multiple tx ring slots rather than
defragging them first.

ok dlg@

Fix receive filter handling. Update the unicast mac address in the filter
when bringing the interface up, so it's possible to change it with
ifconfig. Rearrange multicast handling so IFF_ALLMULTI is set correctly
and multicast ranges don't trigger promisc mode. Perhaps most importantly,
set RPF_MCAST_FILTER_EN to 0 when we don't want all multicast traffic -
we use mac address filters to receive specific multicast groups, and the
multicast filter is programmed to accept all multicast traffic.

based on a diff from Brad
ok dlg@

Invalidate the nic's rx descriptor cache when taking the interface up
or down, and turn off the global tx and rx enables when going down.
Without this, the nic can write to mbufs that were taken off the ring
when the interface was taken down, triggering mbuf cluster pool use
after free checks.

ok dlg@

Handle rxrinfo ioctl.

ok dlg@

No need to enable bus mastering, it's already done for us.

from Brad

wire up bpf correctly

ok dlg@ deraadt@

pci_mapreg_map() will assign an address to the BAR if it doesn't have one
already, so we shouldn't refuse to attach in that case.

noticed by kevlo@ on arm64
ok dlg@ deraadt@

aq(4) driver for Aquantia 1/2.5/5/10Gb/s PCIe ethernet adapters

Adds support for Aquantia AQC1xx family of PCIe ethernet adapters. This
driver supports 1Gbps through 10Gbps modes of operation based on the
hardware and media/switch capabilities.

The initial code was ported from NetBSD, with jmatthew@ finishing up
the Tx/Rx ring support and interrupt handler routine.

The driver only supports devices using firmware V2.

This diff enables aq(4) on riscv64 and amd64, the only platforms where
I have tested the driver, but it likely works on other architectures
as well.

Remove bogus newline in printf.

ok jmatthew@

The built-in 10G Ethernet on Apple arm64 hardware does not have a MAC
address programmed into the hardware. Get it from the device tree instead.

ok dlg@, jmatthew@

Add initial support for Atlantic 2 hardware. Atlantic 2 has
much more complicated rx processing, and here we're doing the
bare minimum to get packets moving. RSS is not implemented yet,
vlans and multicast (among others) probably don't work yet either.

tested by kettenis@ on an M2 Mac Mini, and by me on an AQC113
card provided by Brad
ok dlg@

Adjust some printfs in the attach code path to make more sense,
and include the mac address of the interface on the attach line.

ok dlg@

Prepare for adding Atlantic 2 support by renaming functions and defines
specific to Atlantic 1, shuffling some of the setup code, and adding
get_mac_addr to the firmware ops struct.

ok dlg@

As with if_em.c r1.350, and for the same reasons (arm64 systems with non
cache coherent PCIe), map the rx and tx rings coherent.

tested by kevlo@ on rockpro64
ok dlg@

constify struct cfattach

Add dmamap syncs for rings and mbufs, fixing occasional errors seen
on a rockpro64, where dma is less coherent than on typical amd64 systems.

with and ok dlg@

If we've created multiple queues, set up an RSS key and indirection table
to distribute received packets across the queues.

ok dlg@

If enough MSI-X vectors are available, set up multiple tx and rx queues.
In multi-vector mode, the MSI-X vector number is the same as the irq number
on the nic, so use vector/irq 0 for link interrupts, then assign one to
each pair of rx and tx queues. We don't configure RSS yet, so packets
will only be received on the first queue, but they can be transmitted on
any queue.

ok dlg@

Expand tx dma maps to allow packets up to the MTU limit to be transmitted.
Don't clear TPB_TX_BUF_EN when taking the interface down, as somehow that
causes transmission to fail when the interface comes up again if any large
packets had been sent.

Handle packets received into multiple rx buffers using the same approach as
ixl(4), with the addition that a receive error can be signaled on any of
the buffers rather than just the last one. Set the low water mark on the
rx ring so there are always enough buffers to receive the largest packet
supported by the interface, and fix the calculation of the data pointer
in rx buffers so there's actually MCLBYTES space available.

ok dlg@

Enable interrupt moderation, targeting around 20k interrupts per second.
There are separate timers for rx and tx interrupts, so we can use longer
timeouts for tx since that doesn't affect packet processing latency.

ok dlg@

Enable checksum offloads. The nic does all the work here, so we don't
need to calculate header offsets for it.

ok dlg@

Enable vlan promisc and header stripping, and use vlan rx/tx offloads.
The vlan tx information takes up an extra slot on the tx ring, so this
affects the point at which we stop putting packets on the ring too.

ok dlg@

Transmit segmented packets using multiple tx ring slots rather than
defragging them first.

ok dlg@

Fix receive filter handling. Update the unicast mac address in the filter
when bringing the interface up, so it's possible to change it with
ifconfig. Rearrange multicast handling so IFF_ALLMULTI is set correctly
and multicast ranges don't trigger promisc mode. Perhaps most importantly,
set RPF_MCAST_FILTER_EN to 0 when we don't want all multicast traffic -
we use mac address filters to receive specific multicast groups, and the
multicast filter is programmed to accept all multicast traffic.

based on a diff from Brad
ok dlg@

Invalidate the nic's rx descriptor cache when taking the interface up
or down, and turn off the global tx and rx enables when going down.
Without this, the nic can write to mbufs that were taken off the ring
when the interface was taken down, triggering mbuf cluster pool use
after free checks.

ok dlg@

Handle rxrinfo ioctl.

ok dlg@

No need to enable bus mastering, it's already done for us.

from Brad

wire up bpf correctly

ok dlg@ deraadt@

pci_mapreg_map() will assign an address to the BAR if it doesn't have one
already, so we shouldn't refuse to attach in that case.

noticed by kevlo@ on arm64
ok dlg@ deraadt@

aq(4) driver for Aquantia 1/2.5/5/10Gb/s PCIe ethernet adapters

Adds support for Aquantia AQC1xx family of PCIe ethernet adapters. This
driver supports 1Gbps through 10Gbps modes of operation based on the
hardware and media/switch capabilities.

The initial code was ported from NetBSD, with jmatthew@ finishing up
the Tx/Rx ring support and interrupt handler routine.

The driver only supports devices using firmware V2.

This diff enables aq(4) on riscv64 and amd64, the only platforms where
I have tested the driver, but it likely works on other architectures
as well.

Remove bogus newline in printf.

ok jmatthew@

The built-in 10G Ethernet on Apple arm64 hardware does not have a MAC
address programmed into the hardware. Get it from the device tree instead.

ok dlg@, jmatthew@

Add initial support for Atlantic 2 hardware. Atlantic 2 has
much more complicated rx processing, and here we're doing the
bare minimum to get packets moving. RSS is not implemented yet,
vlans and multicast (among others) probably don't work yet either.

tested by kettenis@ on an M2 Mac Mini, and by me on an AQC113
card provided by Brad
ok dlg@

Adjust some printfs in the attach code path to make more sense,
and include the mac address of the interface on the attach line.

ok dlg@

Prepare for adding Atlantic 2 support by renaming functions and defines
specific to Atlantic 1, shuffling some of the setup code, and adding
get_mac_addr to the firmware ops struct.

ok dlg@

As with if_em.c r1.350, and for the same reasons (arm64 systems with non
cache coherent PCIe), map the rx and tx rings coherent.

tested by kevlo@ on rockpro64
ok dlg@

constify struct cfattach

Add dmamap syncs for rings and mbufs, fixing occasional errors seen
on a rockpro64, where dma is less coherent than on typical amd64 systems.

with and ok dlg@

If we've created multiple queues, set up an RSS key and indirection table
to distribute received packets across the queues.

ok dlg@

If enough MSI-X vectors are available, set up multiple tx and rx queues.
In multi-vector mode, the MSI-X vector number is the same as the irq number
on the nic, so use vector/irq 0 for link interrupts, then assign one to
each pair of rx and tx queues. We don't configure RSS yet, so packets
will only be received on the first queue, but they can be transmitted on
any queue.

ok dlg@

Expand tx dma maps to allow packets up to the MTU limit to be transmitted.
Don't clear TPB_TX_BUF_EN when taking the interface down, as somehow that
causes transmission to fail when the interface comes up again if any large
packets had been sent.

Handle packets received into multiple rx buffers using the same approach as
ixl(4), with the addition that a receive error can be signaled on any of
the buffers rather than just the last one. Set the low water mark on the
rx ring so there are always enough buffers to receive the largest packet
supported by the interface, and fix the calculation of the data pointer
in rx buffers so there's actually MCLBYTES space available.

ok dlg@

Enable interrupt moderation, targeting around 20k interrupts per second.
There are separate timers for rx and tx interrupts, so we can use longer
timeouts for tx since that doesn't affect packet processing latency.

ok dlg@

Enable checksum offloads. The nic does all the work here, so we don't
need to calculate header offsets for it.

ok dlg@

Enable vlan promisc and header stripping, and use vlan rx/tx offloads.
The vlan tx information takes up an extra slot on the tx ring, so this
affects the point at which we stop putting packets on the ring too.

ok dlg@

Transmit segmented packets using multiple tx ring slots rather than
defragging them first.

ok dlg@

Fix receive filter handling. Update the unicast mac address in the filter
when bringing the interface up, so it's possible to change it with
ifconfig. Rearrange multicast handling so IFF_ALLMULTI is set correctly
and multicast ranges don't trigger promisc mode. Perhaps most importantly,
set RPF_MCAST_FILTER_EN to 0 when we don't want all multicast traffic -
we use mac address filters to receive specific multicast groups, and the
multicast filter is programmed to accept all multicast traffic.

based on a diff from Brad
ok dlg@

Invalidate the nic's rx descriptor cache when taking the interface up
or down, and turn off the global tx and rx enables when going down.
Without this, the nic can write to mbufs that were taken off the ring
when the interface was taken down, triggering mbuf cluster pool use
after free checks.

ok dlg@

Handle rxrinfo ioctl.

ok dlg@

No need to enable bus mastering, it's already done for us.

from Brad

wire up bpf correctly

ok dlg@ deraadt@

pci_mapreg_map() will assign an address to the BAR if it doesn't have one
already, so we shouldn't refuse to attach in that case.

noticed by kevlo@ on arm64
ok dlg@ deraadt@

aq(4) driver for Aquantia 1/2.5/5/10Gb/s PCIe ethernet adapters

Adds support for Aquantia AQC1xx family of PCIe ethernet adapters. This
driver supports 1Gbps through 10Gbps modes of operation based on the
hardware and media/switch capabilities.

The initial code was ported from NetBSD, with jmatthew@ finishing up
the Tx/Rx ring support and interrupt handler routine.

The driver only supports devices using firmware V2.

This diff enables aq(4) on riscv64 and amd64, the only platforms where
I have tested the driver, but it likely works on other architectures
as well.

Add initial support for Atlantic 2 hardware. Atlantic 2 has
much more complicated rx processing, and here we're doing the
bare minimum to get packets moving. RSS is not implemented yet,
vlans and multicast (among others) probably don't work yet either.

tested by kettenis@ on an M2 Mac Mini, and by me on an AQC113
card provided by Brad
ok dlg@

Adjust some printfs in the attach code path to make more sense,
and include the mac address of the interface on the attach line.

ok dlg@

Prepare for adding Atlantic 2 support by renaming functions and defines
specific to Atlantic 1, shuffling some of the setup code, and adding
get_mac_addr to the firmware ops struct.

ok dlg@

As with if_em.c r1.350, and for the same reasons (arm64 systems with non
cache coherent PCIe), map the rx and tx rings coherent.

tested by kevlo@ on rockpro64
ok dlg@

constify struct cfattach

Add dmamap syncs for rings and mbufs, fixing occasional errors seen
on a rockpro64, where dma is less coherent than on typical amd64 systems.

with and ok dlg@

If we've created multiple queues, set up an RSS key and indirection table
to distribute received packets across the queues.

ok dlg@

If enough MSI-X vectors are available, set up multiple tx and rx queues.
In multi-vector mode, the MSI-X vector number is the same as the irq number
on the nic, so use vector/irq 0 for link interrupts, then assign one to
each pair of rx and tx queues. We don't configure RSS yet, so packets
will only be received on the first queue, but they can be transmitted on
any queue.

ok dlg@

Expand tx dma maps to allow packets up to the MTU limit to be transmitted.
Don't clear TPB_TX_BUF_EN when taking the interface down, as somehow that
causes transmission to fail when the interface comes up again if any large
packets had been sent.

Handle packets received into multiple rx buffers using the same approach as
ixl(4), with the addition that a receive error can be signaled on any of
the buffers rather than just the last one. Set the low water mark on the
rx ring so there are always enough buffers to receive the largest packet
supported by the interface, and fix the calculation of the data pointer
in rx buffers so there's actually MCLBYTES space available.

ok dlg@

Enable interrupt moderation, targeting around 20k interrupts per second.
There are separate timers for rx and tx interrupts, so we can use longer
timeouts for tx since that doesn't affect packet processing latency.

ok dlg@

Enable checksum offloads. The nic does all the work here, so we don't
need to calculate header offsets for it.

ok dlg@

Enable vlan promisc and header stripping, and use vlan rx/tx offloads.
The vlan tx information takes up an extra slot on the tx ring, so this
affects the point at which we stop putting packets on the ring too.

ok dlg@

Transmit segmented packets using multiple tx ring slots rather than
defragging them first.

ok dlg@

Fix receive filter handling. Update the unicast mac address in the filter
when bringing the interface up, so it's possible to change it with
ifconfig. Rearrange multicast handling so IFF_ALLMULTI is set correctly
and multicast ranges don't trigger promisc mode. Perhaps most importantly,
set RPF_MCAST_FILTER_EN to 0 when we don't want all multicast traffic -
we use mac address filters to receive specific multicast groups, and the
multicast filter is programmed to accept all multicast traffic.

based on a diff from Brad
ok dlg@

Invalidate the nic's rx descriptor cache when taking the interface up
or down, and turn off the global tx and rx enables when going down.
Without this, the nic can write to mbufs that were taken off the ring
when the interface was taken down, triggering mbuf cluster pool use
after free checks.

ok dlg@

Handle rxrinfo ioctl.

ok dlg@

No need to enable bus mastering, it's already done for us.

from Brad

wire up bpf correctly

ok dlg@ deraadt@

pci_mapreg_map() will assign an address to the BAR if it doesn't have one
already, so we shouldn't refuse to attach in that case.

noticed by kevlo@ on arm64
ok dlg@ deraadt@

aq(4) driver for Aquantia 1/2.5/5/10Gb/s PCIe ethernet adapters

Adds support for Aquantia AQC1xx family of PCIe ethernet adapters. This
driver supports 1Gbps through 10Gbps modes of operation based on the
hardware and media/switch capabilities.

The initial code was ported from NetBSD, with jmatthew@ finishing up
the Tx/Rx ring support and interrupt handler routine.

The driver only supports devices using firmware V2.

This diff enables aq(4) on riscv64 and amd64, the only platforms where
I have tested the driver, but it likely works on other architectures
as well.

As with if_em.c r1.350, and for the same reasons (arm64 systems with non
cache coherent PCIe), map the rx and tx rings coherent.

tested by kevlo@ on rockpro64
ok dlg@

constify struct cfattach

Add dmamap syncs for rings and mbufs, fixing occasional errors seen
on a rockpro64, where dma is less coherent than on typical amd64 systems.

with and ok dlg@

If we've created multiple queues, set up an RSS key and indirection table
to distribute received packets across the queues.

ok dlg@

If enough MSI-X vectors are available, set up multiple tx and rx queues.
In multi-vector mode, the MSI-X vector number is the same as the irq number
on the nic, so use vector/irq 0 for link interrupts, then assign one to
each pair of rx and tx queues. We don't configure RSS yet, so packets
will only be received on the first queue, but they can be transmitted on
any queue.

ok dlg@

Expand tx dma maps to allow packets up to the MTU limit to be transmitted.
Don't clear TPB_TX_BUF_EN when taking the interface down, as somehow that
causes transmission to fail when the interface comes up again if any large
packets had been sent.

Handle packets received into multiple rx buffers using the same approach as
ixl(4), with the addition that a receive error can be signaled on any of
the buffers rather than just the last one. Set the low water mark on the
rx ring so there are always enough buffers to receive the largest packet
supported by the interface, and fix the calculation of the data pointer
in rx buffers so there's actually MCLBYTES space available.

ok dlg@

Enable interrupt moderation, targeting around 20k interrupts per second.
There are separate timers for rx and tx interrupts, so we can use longer
timeouts for tx since that doesn't affect packet processing latency.

ok dlg@

Enable checksum offloads. The nic does all the work here, so we don't
need to calculate header offsets for it.

ok dlg@

Enable vlan promisc and header stripping, and use vlan rx/tx offloads.
The vlan tx information takes up an extra slot on the tx ring, so this
affects the point at which we stop putting packets on the ring too.

ok dlg@

Transmit segmented packets using multiple tx ring slots rather than
defragging them first.

ok dlg@

Fix receive filter handling. Update the unicast mac address in the filter
when bringing the interface up, so it's possible to change it with
ifconfig. Rearrange multicast handling so IFF_ALLMULTI is set correctly
and multicast ranges don't trigger promisc mode. Perhaps most importantly,
set RPF_MCAST_FILTER_EN to 0 when we don't want all multicast traffic -
we use mac address filters to receive specific multicast groups, and the
multicast filter is programmed to accept all multicast traffic.

based on a diff from Brad
ok dlg@

Invalidate the nic's rx descriptor cache when taking the interface up
or down, and turn off the global tx and rx enables when going down.
Without this, the nic can write to mbufs that were taken off the ring
when the interface was taken down, triggering mbuf cluster pool use
after free checks.

ok dlg@

Handle rxrinfo ioctl.

ok dlg@

No need to enable bus mastering, it's already done for us.

from Brad

wire up bpf correctly

ok dlg@ deraadt@

pci_mapreg_map() will assign an address to the BAR if it doesn't have one
already, so we shouldn't refuse to attach in that case.

noticed by kevlo@ on arm64
ok dlg@ deraadt@

aq(4) driver for Aquantia 1/2.5/5/10Gb/s PCIe ethernet adapters

Adds support for Aquantia AQC1xx family of PCIe ethernet adapters. This
driver supports 1Gbps through 10Gbps modes of operation based on the
hardware and media/switch capabilities.

The initial code was ported from NetBSD, with jmatthew@ finishing up
the Tx/Rx ring support and interrupt handler routine.

The driver only supports devices using firmware V2.

This diff enables aq(4) on riscv64 and amd64, the only platforms where
I have tested the driver, but it likely works on other architectures
as well.

constify struct cfattach

Add dmamap syncs for rings and mbufs, fixing occasional errors seen
on a rockpro64, where dma is less coherent than on typical amd64 systems.

with and ok dlg@

If we've created multiple queues, set up an RSS key and indirection table
to distribute received packets across the queues.

ok dlg@

If enough MSI-X vectors are available, set up multiple tx and rx queues.
In multi-vector mode, the MSI-X vector number is the same as the irq number
on the nic, so use vector/irq 0 for link interrupts, then assign one to
each pair of rx and tx queues. We don't configure RSS yet, so packets
will only be received on the first queue, but they can be transmitted on
any queue.

ok dlg@

Expand tx dma maps to allow packets up to the MTU limit to be transmitted.
Don't clear TPB_TX_BUF_EN when taking the interface down, as somehow that
causes transmission to fail when the interface comes up again if any large
packets had been sent.

Handle packets received into multiple rx buffers using the same approach as
ixl(4), with the addition that a receive error can be signaled on any of
the buffers rather than just the last one. Set the low water mark on the
rx ring so there are always enough buffers to receive the largest packet
supported by the interface, and fix the calculation of the data pointer
in rx buffers so there's actually MCLBYTES space available.

ok dlg@

Enable interrupt moderation, targeting around 20k interrupts per second.
There are separate timers for rx and tx interrupts, so we can use longer
timeouts for tx since that doesn't affect packet processing latency.

ok dlg@

Enable checksum offloads. The nic does all the work here, so we don't
need to calculate header offsets for it.

ok dlg@

Enable vlan promisc and header stripping, and use vlan rx/tx offloads.
The vlan tx information takes up an extra slot on the tx ring, so this
affects the point at which we stop putting packets on the ring too.

ok dlg@

Transmit segmented packets using multiple tx ring slots rather than
defragging them first.

ok dlg@

Fix receive filter handling. Update the unicast mac address in the filter
when bringing the interface up, so it's possible to change it with
ifconfig. Rearrange multicast handling so IFF_ALLMULTI is set correctly
and multicast ranges don't trigger promisc mode. Perhaps most importantly,
set RPF_MCAST_FILTER_EN to 0 when we don't want all multicast traffic -
we use mac address filters to receive specific multicast groups, and the
multicast filter is programmed to accept all multicast traffic.

based on a diff from Brad
ok dlg@

Invalidate the nic's rx descriptor cache when taking the interface up
or down, and turn off the global tx and rx enables when going down.
Without this, the nic can write to mbufs that were taken off the ring
when the interface was taken down, triggering mbuf cluster pool use
after free checks.

ok dlg@

Handle rxrinfo ioctl.

ok dlg@

No need to enable bus mastering, it's already done for us.

from Brad

wire up bpf correctly

ok dlg@ deraadt@

pci_mapreg_map() will assign an address to the BAR if it doesn't have one
already, so we shouldn't refuse to attach in that case.

noticed by kevlo@ on arm64
ok dlg@ deraadt@

aq(4) driver for Aquantia 1/2.5/5/10Gb/s PCIe ethernet adapters

Adds support for Aquantia AQC1xx family of PCIe ethernet adapters. This
driver supports 1Gbps through 10Gbps modes of operation based on the
hardware and media/switch capabilities.

The initial code was ported from NetBSD, with jmatthew@ finishing up
the Tx/Rx ring support and interrupt handler routine.

The driver only supports devices using firmware V2.

This diff enables aq(4) on riscv64 and amd64, the only platforms where
I have tested the driver, but it likely works on other architectures
as well.

Add dmamap syncs for rings and mbufs, fixing occasional errors seen
on a rockpro64, where dma is less coherent than on typical amd64 systems.

with and ok dlg@

If we've created multiple queues, set up an RSS key and indirection table
to distribute received packets across the queues.

ok dlg@

If enough MSI-X vectors are available, set up multiple tx and rx queues.
In multi-vector mode, the MSI-X vector number is the same as the irq number
on the nic, so use vector/irq 0 for link interrupts, then assign one to
each pair of rx and tx queues. We don't configure RSS yet, so packets
will only be received on the first queue, but they can be transmitted on
any queue.

ok dlg@

Expand tx dma maps to allow packets up to the MTU limit to be transmitted.
Don't clear TPB_TX_BUF_EN when taking the interface down, as somehow that
causes transmission to fail when the interface comes up again if any large
packets had been sent.

Handle packets received into multiple rx buffers using the same approach as
ixl(4), with the addition that a receive error can be signaled on any of
the buffers rather than just the last one. Set the low water mark on the
rx ring so there are always enough buffers to receive the largest packet
supported by the interface, and fix the calculation of the data pointer
in rx buffers so there's actually MCLBYTES space available.

ok dlg@

Enable interrupt moderation, targeting around 20k interrupts per second.
There are separate timers for rx and tx interrupts, so we can use longer
timeouts for tx since that doesn't affect packet processing latency.

ok dlg@

Enable checksum offloads. The nic does all the work here, so we don't
need to calculate header offsets for it.

ok dlg@

Enable vlan promisc and header stripping, and use vlan rx/tx offloads.
The vlan tx information takes up an extra slot on the tx ring, so this
affects the point at which we stop putting packets on the ring too.

ok dlg@

Transmit segmented packets using multiple tx ring slots rather than
defragging them first.

ok dlg@

Fix receive filter handling. Update the unicast mac address in the filter
when bringing the interface up, so it's possible to change it with
ifconfig. Rearrange multicast handling so IFF_ALLMULTI is set correctly
and multicast ranges don't trigger promisc mode. Perhaps most importantly,
set RPF_MCAST_FILTER_EN to 0 when we don't want all multicast traffic -
we use mac address filters to receive specific multicast groups, and the
multicast filter is programmed to accept all multicast traffic.

based on a diff from Brad
ok dlg@

Invalidate the nic's rx descriptor cache when taking the interface up
or down, and turn off the global tx and rx enables when going down.
Without this, the nic can write to mbufs that were taken off the ring
when the interface was taken down, triggering mbuf cluster pool use
after free checks.

ok dlg@

Handle rxrinfo ioctl.

ok dlg@

No need to enable bus mastering, it's already done for us.

from Brad

wire up bpf correctly

ok dlg@ deraadt@

pci_mapreg_map() will assign an address to the BAR if it doesn't have one
already, so we shouldn't refuse to attach in that case.

noticed by kevlo@ on arm64
ok dlg@ deraadt@

aq(4) driver for Aquantia 1/2.5/5/10Gb/s PCIe ethernet adapters

Adds support for Aquantia AQC1xx family of PCIe ethernet adapters. This
driver supports 1Gbps through 10Gbps modes of operation based on the
hardware and media/switch capabilities.

The initial code was ported from NetBSD, with jmatthew@ finishing up
the Tx/Rx ring support and interrupt handler routine.

The driver only supports devices using firmware V2.

This diff enables aq(4) on riscv64 and amd64, the only platforms where
I have tested the driver, but it likely works on other architectures
as well.

If we've created multiple queues, set up an RSS key and indirection table
to distribute received packets across the queues.

ok dlg@

If enough MSI-X vectors are available, set up multiple tx and rx queues.
In multi-vector mode, the MSI-X vector number is the same as the irq number
on the nic, so use vector/irq 0 for link interrupts, then assign one to
each pair of rx and tx queues. We don't configure RSS yet, so packets
will only be received on the first queue, but they can be transmitted on
any queue.

ok dlg@

Expand tx dma maps to allow packets up to the MTU limit to be transmitted.
Don't clear TPB_TX_BUF_EN when taking the interface down, as somehow that
causes transmission to fail when the interface comes up again if any large
packets had been sent.

Handle packets received into multiple rx buffers using the same approach as
ixl(4), with the addition that a receive error can be signaled on any of
the buffers rather than just the last one. Set the low water mark on the
rx ring so there are always enough buffers to receive the largest packet
supported by the interface, and fix the calculation of the data pointer
in rx buffers so there's actually MCLBYTES space available.

ok dlg@

Enable interrupt moderation, targeting around 20k interrupts per second.
There are separate timers for rx and tx interrupts, so we can use longer
timeouts for tx since that doesn't affect packet processing latency.

ok dlg@

Enable checksum offloads. The nic does all the work here, so we don't
need to calculate header offsets for it.

ok dlg@

Enable vlan promisc and header stripping, and use vlan rx/tx offloads.
The vlan tx information takes up an extra slot on the tx ring, so this
affects the point at which we stop putting packets on the ring too.

ok dlg@

Transmit segmented packets using multiple tx ring slots rather than
defragging them first.

ok dlg@

Fix receive filter handling. Update the unicast mac address in the filter
when bringing the interface up, so it's possible to change it with
ifconfig. Rearrange multicast handling so IFF_ALLMULTI is set correctly
and multicast ranges don't trigger promisc mode. Perhaps most importantly,
set RPF_MCAST_FILTER_EN to 0 when we don't want all multicast traffic -
we use mac address filters to receive specific multicast groups, and the
multicast filter is programmed to accept all multicast traffic.

based on a diff from Brad
ok dlg@

Invalidate the nic's rx descriptor cache when taking the interface up
or down, and turn off the global tx and rx enables when going down.
Without this, the nic can write to mbufs that were taken off the ring
when the interface was taken down, triggering mbuf cluster pool use
after free checks.

ok dlg@

Handle rxrinfo ioctl.

ok dlg@

No need to enable bus mastering, it's already done for us.

from Brad

wire up bpf correctly

ok dlg@ deraadt@

pci_mapreg_map() will assign an address to the BAR if it doesn't have one
already, so we shouldn't refuse to attach in that case.

noticed by kevlo@ on arm64
ok dlg@ deraadt@

aq(4) driver for Aquantia 1/2.5/5/10Gb/s PCIe ethernet adapters

Adds support for Aquantia AQC1xx family of PCIe ethernet adapters. This
driver supports 1Gbps through 10Gbps modes of operation based on the
hardware and media/switch capabilities.

The initial code was ported from NetBSD, with jmatthew@ finishing up
the Tx/Rx ring support and interrupt handler routine.

The driver only supports devices using firmware V2.

This diff enables aq(4) on riscv64 and amd64, the only platforms where
I have tested the driver, but it likely works on other architectures
as well.

If enough MSI-X vectors are available, set up multiple tx and rx queues.
In multi-vector mode, the MSI-X vector number is the same as the irq number
on the nic, so use vector/irq 0 for link interrupts, then assign one to
each pair of rx and tx queues. We don't configure RSS yet, so packets
will only be received on the first queue, but they can be transmitted on
any queue.

ok dlg@

Expand tx dma maps to allow packets up to the MTU limit to be transmitted.
Don't clear TPB_TX_BUF_EN when taking the interface down, as somehow that
causes transmission to fail when the interface comes up again if any large
packets had been sent.

Handle packets received into multiple rx buffers using the same approach as
ixl(4), with the addition that a receive error can be signaled on any of
the buffers rather than just the last one. Set the low water mark on the
rx ring so there are always enough buffers to receive the largest packet
supported by the interface, and fix the calculation of the data pointer
in rx buffers so there's actually MCLBYTES space available.

ok dlg@

Enable interrupt moderation, targeting around 20k interrupts per second.
There are separate timers for rx and tx interrupts, so we can use longer
timeouts for tx since that doesn't affect packet processing latency.

ok dlg@

Enable checksum offloads. The nic does all the work here, so we don't
need to calculate header offsets for it.

ok dlg@

Enable vlan promisc and header stripping, and use vlan rx/tx offloads.
The vlan tx information takes up an extra slot on the tx ring, so this
affects the point at which we stop putting packets on the ring too.

ok dlg@

Transmit segmented packets using multiple tx ring slots rather than
defragging them first.

ok dlg@

Fix receive filter handling. Update the unicast mac address in the filter
when bringing the interface up, so it's possible to change it with
ifconfig. Rearrange multicast handling so IFF_ALLMULTI is set correctly
and multicast ranges don't trigger promisc mode. Perhaps most importantly,
set RPF_MCAST_FILTER_EN to 0 when we don't want all multicast traffic -
we use mac address filters to receive specific multicast groups, and the
multicast filter is programmed to accept all multicast traffic.

based on a diff from Brad
ok dlg@

Invalidate the nic's rx descriptor cache when taking the interface up
or down, and turn off the global tx and rx enables when going down.
Without this, the nic can write to mbufs that were taken off the ring
when the interface was taken down, triggering mbuf cluster pool use
after free checks.

ok dlg@

Handle rxrinfo ioctl.

ok dlg@

No need to enable bus mastering, it's already done for us.

from Brad

wire up bpf correctly

ok dlg@ deraadt@

pci_mapreg_map() will assign an address to the BAR if it doesn't have one
already, so we shouldn't refuse to attach in that case.

noticed by kevlo@ on arm64
ok dlg@ deraadt@

aq(4) driver for Aquantia 1/2.5/5/10Gb/s PCIe ethernet adapters

Adds support for Aquantia AQC1xx family of PCIe ethernet adapters. This
driver supports 1Gbps through 10Gbps modes of operation based on the
hardware and media/switch capabilities.

The initial code was ported from NetBSD, with jmatthew@ finishing up
the Tx/Rx ring support and interrupt handler routine.

The driver only supports devices using firmware V2.

This diff enables aq(4) on riscv64 and amd64, the only platforms where
I have tested the driver, but it likely works on other architectures
as well.

Expand tx dma maps to allow packets up to the MTU limit to be transmitted.
Don't clear TPB_TX_BUF_EN when taking the interface down, as somehow that
causes transmission to fail when the interface comes up again if any large
packets had been sent.

Handle packets received into multiple rx buffers using the same approach as
ixl(4), with the addition that a receive error can be signaled on any of
the buffers rather than just the last one. Set the low water mark on the
rx ring so there are always enough buffers to receive the largest packet
supported by the interface, and fix the calculation of the data pointer
in rx buffers so there's actually MCLBYTES space available.

ok dlg@

Enable interrupt moderation, targeting around 20k interrupts per second.
There are separate timers for rx and tx interrupts, so we can use longer
timeouts for tx since that doesn't affect packet processing latency.

ok dlg@

Enable checksum offloads. The nic does all the work here, so we don't
need to calculate header offsets for it.

ok dlg@

Enable vlan promisc and header stripping, and use vlan rx/tx offloads.
The vlan tx information takes up an extra slot on the tx ring, so this
affects the point at which we stop putting packets on the ring too.

ok dlg@

Transmit segmented packets using multiple tx ring slots rather than
defragging them first.

ok dlg@

Fix receive filter handling. Update the unicast mac address in the filter
when bringing the interface up, so it's possible to change it with
ifconfig. Rearrange multicast handling so IFF_ALLMULTI is set correctly
and multicast ranges don't trigger promisc mode. Perhaps most importantly,
set RPF_MCAST_FILTER_EN to 0 when we don't want all multicast traffic -
we use mac address filters to receive specific multicast groups, and the
multicast filter is programmed to accept all multicast traffic.

based on a diff from Brad
ok dlg@

Invalidate the nic's rx descriptor cache when taking the interface up
or down, and turn off the global tx and rx enables when going down.
Without this, the nic can write to mbufs that were taken off the ring
when the interface was taken down, triggering mbuf cluster pool use
after free checks.

ok dlg@

Handle rxrinfo ioctl.

ok dlg@

No need to enable bus mastering, it's already done for us.

from Brad

wire up bpf correctly

ok dlg@ deraadt@

pci_mapreg_map() will assign an address to the BAR if it doesn't have one
already, so we shouldn't refuse to attach in that case.

noticed by kevlo@ on arm64
ok dlg@ deraadt@

aq(4) driver for Aquantia 1/2.5/5/10Gb/s PCIe ethernet adapters

Adds support for Aquantia AQC1xx family of PCIe ethernet adapters. This
driver supports 1Gbps through 10Gbps modes of operation based on the
hardware and media/switch capabilities.

The initial code was ported from NetBSD, with jmatthew@ finishing up
the Tx/Rx ring support and interrupt handler routine.

The driver only supports devices using firmware V2.

This diff enables aq(4) on riscv64 and amd64, the only platforms where
I have tested the driver, but it likely works on other architectures
as well.

Enable interrupt moderation, targeting around 20k interrupts per second.
There are separate timers for rx and tx interrupts, so we can use longer
timeouts for tx since that doesn't affect packet processing latency.

ok dlg@

Enable checksum offloads. The nic does all the work here, so we don't
need to calculate header offsets for it.

ok dlg@

Enable vlan promisc and header stripping, and use vlan rx/tx offloads.
The vlan tx information takes up an extra slot on the tx ring, so this
affects the point at which we stop putting packets on the ring too.

ok dlg@

Transmit segmented packets using multiple tx ring slots rather than
defragging them first.

ok dlg@

Fix receive filter handling. Update the unicast mac address in the filter
when bringing the interface up, so it's possible to change it with
ifconfig. Rearrange multicast handling so IFF_ALLMULTI is set correctly
and multicast ranges don't trigger promisc mode. Perhaps most importantly,
set RPF_MCAST_FILTER_EN to 0 when we don't want all multicast traffic -
we use mac address filters to receive specific multicast groups, and the
multicast filter is programmed to accept all multicast traffic.

based on a diff from Brad
ok dlg@

Invalidate the nic's rx descriptor cache when taking the interface up
or down, and turn off the global tx and rx enables when going down.
Without this, the nic can write to mbufs that were taken off the ring
when the interface was taken down, triggering mbuf cluster pool use
after free checks.

ok dlg@

Handle rxrinfo ioctl.

ok dlg@

No need to enable bus mastering, it's already done for us.

from Brad

wire up bpf correctly

ok dlg@ deraadt@

pci_mapreg_map() will assign an address to the BAR if it doesn't have one
already, so we shouldn't refuse to attach in that case.

noticed by kevlo@ on arm64
ok dlg@ deraadt@

aq(4) driver for Aquantia 1/2.5/5/10Gb/s PCIe ethernet adapters

Adds support for Aquantia AQC1xx family of PCIe ethernet adapters. This
driver supports 1Gbps through 10Gbps modes of operation based on the
hardware and media/switch capabilities.

The initial code was ported from NetBSD, with jmatthew@ finishing up
the Tx/Rx ring support and interrupt handler routine.

The driver only supports devices using firmware V2.

This diff enables aq(4) on riscv64 and amd64, the only platforms where
I have tested the driver, but it likely works on other architectures
as well.

Enable checksum offloads. The nic does all the work here, so we don't
need to calculate header offsets for it.

ok dlg@

Enable vlan promisc and header stripping, and use vlan rx/tx offloads.
The vlan tx information takes up an extra slot on the tx ring, so this
affects the point at which we stop putting packets on the ring too.

ok dlg@

Transmit segmented packets using multiple tx ring slots rather than
defragging them first.

ok dlg@

Fix receive filter handling. Update the unicast mac address in the filter
when bringing the interface up, so it's possible to change it with
ifconfig. Rearrange multicast handling so IFF_ALLMULTI is set correctly
and multicast ranges don't trigger promisc mode. Perhaps most importantly,
set RPF_MCAST_FILTER_EN to 0 when we don't want all multicast traffic -
we use mac address filters to receive specific multicast groups, and the
multicast filter is programmed to accept all multicast traffic.

based on a diff from Brad
ok dlg@

Invalidate the nic's rx descriptor cache when taking the interface up
or down, and turn off the global tx and rx enables when going down.
Without this, the nic can write to mbufs that were taken off the ring
when the interface was taken down, triggering mbuf cluster pool use
after free checks.

ok dlg@

Handle rxrinfo ioctl.

ok dlg@

No need to enable bus mastering, it's already done for us.

from Brad

wire up bpf correctly

ok dlg@ deraadt@

pci_mapreg_map() will assign an address to the BAR if it doesn't have one
already, so we shouldn't refuse to attach in that case.

noticed by kevlo@ on arm64
ok dlg@ deraadt@

aq(4) driver for Aquantia 1/2.5/5/10Gb/s PCIe ethernet adapters

Adds support for Aquantia AQC1xx family of PCIe ethernet adapters. This
driver supports 1Gbps through 10Gbps modes of operation based on the
hardware and media/switch capabilities.

The initial code was ported from NetBSD, with jmatthew@ finishing up
the Tx/Rx ring support and interrupt handler routine.

The driver only supports devices using firmware V2.

This diff enables aq(4) on riscv64 and amd64, the only platforms where
I have tested the driver, but it likely works on other architectures
as well.

Enable vlan promisc and header stripping, and use vlan rx/tx offloads.
The vlan tx information takes up an extra slot on the tx ring, so this
affects the point at which we stop putting packets on the ring too.

ok dlg@

Transmit segmented packets using multiple tx ring slots rather than
defragging them first.

ok dlg@

Fix receive filter handling. Update the unicast mac address in the filter
when bringing the interface up, so it's possible to change it with
ifconfig. Rearrange multicast handling so IFF_ALLMULTI is set correctly
and multicast ranges don't trigger promisc mode. Perhaps most importantly,
set RPF_MCAST_FILTER_EN to 0 when we don't want all multicast traffic -
we use mac address filters to receive specific multicast groups, and the
multicast filter is programmed to accept all multicast traffic.

based on a diff from Brad
ok dlg@

Invalidate the nic's rx descriptor cache when taking the interface up
or down, and turn off the global tx and rx enables when going down.
Without this, the nic can write to mbufs that were taken off the ring
when the interface was taken down, triggering mbuf cluster pool use
after free checks.

ok dlg@

Handle rxrinfo ioctl.

ok dlg@

No need to enable bus mastering, it's already done for us.

from Brad

wire up bpf correctly

ok dlg@ deraadt@

pci_mapreg_map() will assign an address to the BAR if it doesn't have one
already, so we shouldn't refuse to attach in that case.

noticed by kevlo@ on arm64
ok dlg@ deraadt@

aq(4) driver for Aquantia 1/2.5/5/10Gb/s PCIe ethernet adapters

Adds support for Aquantia AQC1xx family of PCIe ethernet adapters. This
driver supports 1Gbps through 10Gbps modes of operation based on the
hardware and media/switch capabilities.

The initial code was ported from NetBSD, with jmatthew@ finishing up
the Tx/Rx ring support and interrupt handler routine.

The driver only supports devices using firmware V2.

This diff enables aq(4) on riscv64 and amd64, the only platforms where
I have tested the driver, but it likely works on other architectures
as well.

Fix receive filter handling. Update the unicast mac address in the filter
when bringing the interface up, so it's possible to change it with
ifconfig. Rearrange multicast handling so IFF_ALLMULTI is set correctly
and multicast ranges don't trigger promisc mode. Perhaps most importantly,
set RPF_MCAST_FILTER_EN to 0 when we don't want all multicast traffic -
we use mac address filters to receive specific multicast groups, and the
multicast filter is programmed to accept all multicast traffic.

based on a diff from Brad
ok dlg@

Invalidate the nic's rx descriptor cache when taking the interface up
or down, and turn off the global tx and rx enables when going down.
Without this, the nic can write to mbufs that were taken off the ring
when the interface was taken down, triggering mbuf cluster pool use
after free checks.

ok dlg@

Handle rxrinfo ioctl.

ok dlg@

No need to enable bus mastering, it's already done for us.

from Brad

wire up bpf correctly

ok dlg@ deraadt@

pci_mapreg_map() will assign an address to the BAR if it doesn't have one
already, so we shouldn't refuse to attach in that case.

noticed by kevlo@ on arm64
ok dlg@ deraadt@

aq(4) driver for Aquantia 1/2.5/5/10Gb/s PCIe ethernet adapters

Adds support for Aquantia AQC1xx family of PCIe ethernet adapters. This
driver supports 1Gbps through 10Gbps modes of operation based on the
hardware and media/switch capabilities.

The initial code was ported from NetBSD, with jmatthew@ finishing up
the Tx/Rx ring support and interrupt handler routine.

The driver only supports devices using firmware V2.

This diff enables aq(4) on riscv64 and amd64, the only platforms where
I have tested the driver, but it likely works on other architectures
as well.

Invalidate the nic's rx descriptor cache when taking the interface up
or down, and turn off the global tx and rx enables when going down.
Without this, the nic can write to mbufs that were taken off the ring
when the interface was taken down, triggering mbuf cluster pool use
after free checks.

ok dlg@

Handle rxrinfo ioctl.

ok dlg@

No need to enable bus mastering, it's already done for us.

from Brad

wire up bpf correctly

ok dlg@ deraadt@

pci_mapreg_map() will assign an address to the BAR if it doesn't have one
already, so we shouldn't refuse to attach in that case.

noticed by kevlo@ on arm64
ok dlg@ deraadt@

aq(4) driver for Aquantia 1/2.5/5/10Gb/s PCIe ethernet adapters

Adds support for Aquantia AQC1xx family of PCIe ethernet adapters. This
driver supports 1Gbps through 10Gbps modes of operation based on the
hardware and media/switch capabilities.

The initial code was ported from NetBSD, with jmatthew@ finishing up
the Tx/Rx ring support and interrupt handler routine.

The driver only supports devices using firmware V2.

This diff enables aq(4) on riscv64 and amd64, the only platforms where
I have tested the driver, but it likely works on other architectures
as well.

Handle rxrinfo ioctl.

ok dlg@

No need to enable bus mastering, it's already done for us.

from Brad

wire up bpf correctly

ok dlg@ deraadt@

pci_mapreg_map() will assign an address to the BAR if it doesn't have one
already, so we shouldn't refuse to attach in that case.

noticed by kevlo@ on arm64
ok dlg@ deraadt@

aq(4) driver for Aquantia 1/2.5/5/10Gb/s PCIe ethernet adapters

Adds support for Aquantia AQC1xx family of PCIe ethernet adapters. This
driver supports 1Gbps through 10Gbps modes of operation based on the
hardware and media/switch capabilities.

The initial code was ported from NetBSD, with jmatthew@ finishing up
the Tx/Rx ring support and interrupt handler routine.

The driver only supports devices using firmware V2.

This diff enables aq(4) on riscv64 and amd64, the only platforms where
I have tested the driver, but it likely works on other architectures
as well.

No need to enable bus mastering, it's already done for us.

from Brad

wire up bpf correctly

ok dlg@ deraadt@

pci_mapreg_map() will assign an address to the BAR if it doesn't have one
already, so we shouldn't refuse to attach in that case.

noticed by kevlo@ on arm64
ok dlg@ deraadt@

aq(4) driver for Aquantia 1/2.5/5/10Gb/s PCIe ethernet adapters

Adds support for Aquantia AQC1xx family of PCIe ethernet adapters. This
driver supports 1Gbps through 10Gbps modes of operation based on the
hardware and media/switch capabilities.

The initial code was ported from NetBSD, with jmatthew@ finishing up
the Tx/Rx ring support and interrupt handler routine.

The driver only supports devices using firmware V2.

This diff enables aq(4) on riscv64 and amd64, the only platforms where
I have tested the driver, but it likely works on other architectures
as well.

wire up bpf correctly

ok dlg@ deraadt@

pci_mapreg_map() will assign an address to the BAR if it doesn't have one
already, so we shouldn't refuse to attach in that case.

noticed by kevlo@ on arm64
ok dlg@ deraadt@

aq(4) driver for Aquantia 1/2.5/5/10Gb/s PCIe ethernet adapters

Adds support for Aquantia AQC1xx family of PCIe ethernet adapters. This
driver supports 1Gbps through 10Gbps modes of operation based on the
hardware and media/switch capabilities.

The initial code was ported from NetBSD, with jmatthew@ finishing up
the Tx/Rx ring support and interrupt handler routine.

The driver only supports devices using firmware V2.

This diff enables aq(4) on riscv64 and amd64, the only platforms where
I have tested the driver, but it likely works on other architectures
as well.

aq(4) driver for Aquantia 1/2.5/5/10Gb/s PCIe ethernet adapters

Adds support for Aquantia AQC1xx family of PCIe ethernet adapters. This
driver supports 1Gbps through 10Gbps modes of operation based on the
hardware and media/switch capabilities.

The initial code was ported from NetBSD, with jmatthew@ finishing up
the Tx/Rx ring support and interrupt handler routine.

The driver only supports devices using firmware V2.

This diff enables aq(4) on riscv64 and amd64, the only platforms where
I have tested the driver, but it likely works on other architectures
as well.