Constify struct cfattach.

ok visa@ a long time ago, ok patrick@

Make sure to skip attaching disabled I2C devices. This can happen on
hardware which include a common parent block in their device trees and
only enable the components that were actually implemented, as seen on
e.g. the NanoPi R4S.

Register sxitwi(4) in the I2C framework.

ok kettenis@

Unify messaged printed when we can't estiblish an interrupt.

Pointed out by Artturi Alm.

Give the FDT interrupt API a more generic naming by replacing the
arm_intr_* prefix with fdt_intr_*.

ok kettenis@

Add support for the i2c controller on the Marvell ARMADA 7K/8K SoC as well.

ok patrick@

The I2C controller on the Allwinner hardware is actually a modified
Marvell controller. The difference is essentially register offsets
and a clock divider calculation based on a power of two. Also this
particular hardware needs a delay after sending a stop and before
reading the status register since apparently the data doesn't
propagate fast enough. This makes sxitwi(4) work on the Marvell
Armada 38x.

ok kettenis@

Set the proper bus clock rate based on the "clock-frequency" property and
the rate of the parent clock. If the "clock-frequency" property isn't
present, use the default standard mode clock of 100kHz.

Remove unnecessary delays. There is no reason to wait after each and every
read or write to aregister. There is also no reason to wait after
transmitting a STOP since the controller will wait until the bus is free
when transmitting the next START. Based on a diff by Stephen Graf.

Also remove the interrupt code; it doesn't work on the newer variants of
the device. The functionality will be put back in a future commit.

ok patrick@

Somewhow I botched rev 1.3, which has a = where a |= is needed. Fix this.

Remove duplicate includes from sxitwi(4)

From Artturi Alm

Add support for the i2c controller variant found on the Allwinner A31 and
above and enable the driver on arm64.

From Artturi Alm. Tested by Stephen Graf.

Add missing pipe in sxitwi(4)'s match code to actually make
it a logical OR intead of a binary OR.

From Artturi Alm

Add sxitwi(4), a driver for the (i2c compatible) two-wire bus found on
several Allwinner SoCs. From Artturi Alm, based on code from NetBSD.

Also add axppmic(4), a driver for the AXP209 i2c PMIC, which provides
power down support. Written by Artturi Alm.

Make sure to skip attaching disabled I2C devices. This can happen on
hardware which include a common parent block in their device trees and
only enable the components that were actually implemented, as seen on
e.g. the NanoPi R4S.

Register sxitwi(4) in the I2C framework.

ok kettenis@

Unify messaged printed when we can't estiblish an interrupt.

Pointed out by Artturi Alm.

Give the FDT interrupt API a more generic naming by replacing the
arm_intr_* prefix with fdt_intr_*.

ok kettenis@

Add support for the i2c controller on the Marvell ARMADA 7K/8K SoC as well.

ok patrick@

The I2C controller on the Allwinner hardware is actually a modified
Marvell controller. The difference is essentially register offsets
and a clock divider calculation based on a power of two. Also this
particular hardware needs a delay after sending a stop and before
reading the status register since apparently the data doesn't
propagate fast enough. This makes sxitwi(4) work on the Marvell
Armada 38x.

ok kettenis@

Set the proper bus clock rate based on the "clock-frequency" property and
the rate of the parent clock. If the "clock-frequency" property isn't
present, use the default standard mode clock of 100kHz.

Remove unnecessary delays. There is no reason to wait after each and every
read or write to aregister. There is also no reason to wait after
transmitting a STOP since the controller will wait until the bus is free
when transmitting the next START. Based on a diff by Stephen Graf.

Also remove the interrupt code; it doesn't work on the newer variants of
the device. The functionality will be put back in a future commit.

ok patrick@

Somewhow I botched rev 1.3, which has a = where a |= is needed. Fix this.

Remove duplicate includes from sxitwi(4)

From Artturi Alm

Add support for the i2c controller variant found on the Allwinner A31 and
above and enable the driver on arm64.

From Artturi Alm. Tested by Stephen Graf.

Add missing pipe in sxitwi(4)'s match code to actually make
it a logical OR intead of a binary OR.

From Artturi Alm

Add sxitwi(4), a driver for the (i2c compatible) two-wire bus found on
several Allwinner SoCs. From Artturi Alm, based on code from NetBSD.

Also add axppmic(4), a driver for the AXP209 i2c PMIC, which provides
power down support. Written by Artturi Alm.

Register sxitwi(4) in the I2C framework.

ok kettenis@

Unify messaged printed when we can't estiblish an interrupt.

Pointed out by Artturi Alm.

Give the FDT interrupt API a more generic naming by replacing the
arm_intr_* prefix with fdt_intr_*.

ok kettenis@

Add support for the i2c controller on the Marvell ARMADA 7K/8K SoC as well.

ok patrick@

The I2C controller on the Allwinner hardware is actually a modified
Marvell controller. The difference is essentially register offsets
and a clock divider calculation based on a power of two. Also this
particular hardware needs a delay after sending a stop and before
reading the status register since apparently the data doesn't
propagate fast enough. This makes sxitwi(4) work on the Marvell
Armada 38x.

ok kettenis@

Set the proper bus clock rate based on the "clock-frequency" property and
the rate of the parent clock. If the "clock-frequency" property isn't
present, use the default standard mode clock of 100kHz.

Remove unnecessary delays. There is no reason to wait after each and every
read or write to aregister. There is also no reason to wait after
transmitting a STOP since the controller will wait until the bus is free
when transmitting the next START. Based on a diff by Stephen Graf.

Also remove the interrupt code; it doesn't work on the newer variants of
the device. The functionality will be put back in a future commit.

ok patrick@

Somewhow I botched rev 1.3, which has a = where a |= is needed. Fix this.

Remove duplicate includes from sxitwi(4)

From Artturi Alm

Add support for the i2c controller variant found on the Allwinner A31 and
above and enable the driver on arm64.

From Artturi Alm. Tested by Stephen Graf.

Add missing pipe in sxitwi(4)'s match code to actually make
it a logical OR intead of a binary OR.

From Artturi Alm

Add sxitwi(4), a driver for the (i2c compatible) two-wire bus found on
several Allwinner SoCs. From Artturi Alm, based on code from NetBSD.

Also add axppmic(4), a driver for the AXP209 i2c PMIC, which provides
power down support. Written by Artturi Alm.

Unify messaged printed when we can't estiblish an interrupt.

Pointed out by Artturi Alm.

Give the FDT interrupt API a more generic naming by replacing the
arm_intr_* prefix with fdt_intr_*.

ok kettenis@

Add support for the i2c controller on the Marvell ARMADA 7K/8K SoC as well.

ok patrick@

The I2C controller on the Allwinner hardware is actually a modified
Marvell controller. The difference is essentially register offsets
and a clock divider calculation based on a power of two. Also this
particular hardware needs a delay after sending a stop and before
reading the status register since apparently the data doesn't
propagate fast enough. This makes sxitwi(4) work on the Marvell
Armada 38x.

ok kettenis@

Set the proper bus clock rate based on the "clock-frequency" property and
the rate of the parent clock. If the "clock-frequency" property isn't
present, use the default standard mode clock of 100kHz.

Remove unnecessary delays. There is no reason to wait after each and every
read or write to aregister. There is also no reason to wait after
transmitting a STOP since the controller will wait until the bus is free
when transmitting the next START. Based on a diff by Stephen Graf.

Also remove the interrupt code; it doesn't work on the newer variants of
the device. The functionality will be put back in a future commit.

ok patrick@

Somewhow I botched rev 1.3, which has a = where a |= is needed. Fix this.

Remove duplicate includes from sxitwi(4)

From Artturi Alm

Add support for the i2c controller variant found on the Allwinner A31 and
above and enable the driver on arm64.

From Artturi Alm. Tested by Stephen Graf.

Add missing pipe in sxitwi(4)'s match code to actually make
it a logical OR intead of a binary OR.

From Artturi Alm

Add sxitwi(4), a driver for the (i2c compatible) two-wire bus found on
several Allwinner SoCs. From Artturi Alm, based on code from NetBSD.

Also add axppmic(4), a driver for the AXP209 i2c PMIC, which provides
power down support. Written by Artturi Alm.

Give the FDT interrupt API a more generic naming by replacing the
arm_intr_* prefix with fdt_intr_*.

ok kettenis@

Add support for the i2c controller on the Marvell ARMADA 7K/8K SoC as well.

ok patrick@

The I2C controller on the Allwinner hardware is actually a modified
Marvell controller. The difference is essentially register offsets
and a clock divider calculation based on a power of two. Also this
particular hardware needs a delay after sending a stop and before
reading the status register since apparently the data doesn't
propagate fast enough. This makes sxitwi(4) work on the Marvell
Armada 38x.

ok kettenis@

Set the proper bus clock rate based on the "clock-frequency" property and
the rate of the parent clock. If the "clock-frequency" property isn't
present, use the default standard mode clock of 100kHz.

Remove unnecessary delays. There is no reason to wait after each and every
read or write to aregister. There is also no reason to wait after
transmitting a STOP since the controller will wait until the bus is free
when transmitting the next START. Based on a diff by Stephen Graf.

Also remove the interrupt code; it doesn't work on the newer variants of
the device. The functionality will be put back in a future commit.

ok patrick@

Somewhow I botched rev 1.3, which has a = where a |= is needed. Fix this.

Remove duplicate includes from sxitwi(4)

From Artturi Alm

Add support for the i2c controller variant found on the Allwinner A31 and
above and enable the driver on arm64.

From Artturi Alm. Tested by Stephen Graf.

Add missing pipe in sxitwi(4)'s match code to actually make
it a logical OR intead of a binary OR.

From Artturi Alm

Add sxitwi(4), a driver for the (i2c compatible) two-wire bus found on
several Allwinner SoCs. From Artturi Alm, based on code from NetBSD.

Also add axppmic(4), a driver for the AXP209 i2c PMIC, which provides
power down support. Written by Artturi Alm.

Set the proper bus clock rate based on the "clock-frequency" property and
the rate of the parent clock. If the "clock-frequency" property isn't
present, use the default standard mode clock of 100kHz.

Remove unnecessary delays. There is no reason to wait after each and every
read or write to aregister. There is also no reason to wait after
transmitting a STOP since the controller will wait until the bus is free
when transmitting the next START. Based on a diff by Stephen Graf.

Also remove the interrupt code; it doesn't work on the newer variants of
the device. The functionality will be put back in a future commit.

ok patrick@

Somewhow I botched rev 1.3, which has a = where a |= is needed. Fix this.

Remove duplicate includes from sxitwi(4)

From Artturi Alm

Add support for the i2c controller variant found on the Allwinner A31 and
above and enable the driver on arm64.

From Artturi Alm. Tested by Stephen Graf.

Add missing pipe in sxitwi(4)'s match code to actually make
it a logical OR intead of a binary OR.

From Artturi Alm

Add sxitwi(4), a driver for the (i2c compatible) two-wire bus found on
several Allwinner SoCs. From Artturi Alm, based on code from NetBSD.

Also add axppmic(4), a driver for the AXP209 i2c PMIC, which provides
power down support. Written by Artturi Alm.