Now that we support RISC-V CPUs that have MMUs with memory cachability
attributes, the "direct map" becomes problematic as it results in
mappings for the same physical memory pages with different cachability
addresses. The RISC-V specification of the "Svpbmt" extension doesn't
outright state that this is "verboten" like on some other
architectures that we support. But it does say that it may result in
access with the wrong attributes. So restrict the use of the direct
map to just mapping the 64MB block that the bootloader loaded us into.
To make this possible map the device tree later like we do on arm64.
This allows us to get rid of some assembly code in locore.S as a bonus!

ok miod@, jca@

The devicetree standard allows for multiple /memory nodes, each with
multiple memory ranges. We support the latter, but not the former.
Fix this, such that we detect all the memory on the Milk-V Pioneer
board.

ok miod@

revert r1.35

i dont know what i'm doing wrong with the handling of the no-map
property, but i'll find some coffee and time and figure it out soon
hopefully.

handle /reserved-memory nodes from device trees on arm64.

u-boot is supposed to take these entries and put them in the efi
memory map, but i keep hitting machines where an otherwise functional
u-boot does not do this, resulting in weird errors.

i have an espressobin with a vendor u-boot that has a reserved-memory
region for psci. without this diff the machine faults when the
kernel tries to reboot using a psci handler.

a macchiatobin with an otherwise working u-boot throws SErrors or
panics on weird memory corruption problems without this. i thought
it was bad RAM, but the problems persisted with completely different
ram, and very underclocked and well cooled ram.

riscv64 already has code to handle reserved-memory regions. the
riscv64 change is to add handling for the "no-map" property.

ok kettenis@

T-Head implemented a page attribute extension that violates the RISC-V
specification. The default attributes result in memory being uncached
which makes the system perform like a slug. So implement a workaround
that is designed to make implementation of the Svpbmt extension that is
part of the latest published RISC-V specification. This gets us a bit
further booting OpenBSD on an Allwinner D1 SoC.

ok mlarkin@, jca@

Account for nkmempages as well in the pmap_growkernel() call during
initalisation. This way there is enough KVA mapped that kmeminit()
succeeds even with large nkmempages. This is similar to e.g. alpha.
OK miod@ kettenis@

Skip leading dash in kernel boot options instead of complaining it is an
unknown option character.

cpu_idle_{enter,leave} are no-ops on riscv64, so just #define
away the calls

ok jca@

Print SBI vendor, version and implemented spec version

On my Unmatched:

SBI: OpenSBI v0.9, SBI Specification Version 0.2

ok mlarkin@

Simplfity setregs() by passing it the ps_strings and switching
sys_execve() to return EJUSTRETURN.

setregs() is the MD routine used by sys_execve() to set up the
thread's trapframe and PCB such that, on 'return' to userspace, it
has the register values defined by the ABI and otherwise zero. It
had to set the syscall retval[] values previously because the normal
syscall return path overwrites a couple registers with the retval[]
values. By instead returning EJUSTRETURN that and some complexity
with program-counter handling on m88k and sparc64 goes away.

Also, give setregs() add a 'struct ps_strings *arginfo' argument
so powerpc, powerpc64, and sh can directly get argc/argv/envp
values for registers instead of copyin()ing the one in userspace.

Improvements from miod@ and millert@
Testing assistance miod@, kettenis@, and aoyama@
ok miod@ kettenis@

Reorganize the EFI code a bit. Move the efi.h header from dev/acpi to
dev/efi and rename the arm64 efi.c to efi_machdep.c, preparing the way
for MI EFI code and an amd64 implementation of EFI runtime support.

ok deraadt@, mlarkin@

Do not bother initializing a0 with a special value in setregs, that's a
FreeBSDism we have no need for.
ok jsg@

Provide instruction cache invalidation through sysarch(RISCV_ICACHE_SYNC)

Modelled after the arm implementation. The first consumer would be
__builtin___clear_cache() in libcompiler_rt.

Input from kettenis@ and deraadt@, ok kettenis@

Remove a few pointless comments.

Cleanup early bootstrap code. This mostly realigns the code with the
FreeBSD code from which it was derived. In particular, it uses the same
trick to switch page tables as FreeBSD, which is what we use to spin up
the secondary CPUs already. This avoids having to install a temporary
1:1 mapping.

ok mlarkin@

Simplify the way we track the FPU state, using powerpc64 as a model.
The new code still uses the clean/dirty state that the hardware reports
to optimize saving/restoring the FPU register, but no longer attempts to
keep the FPU registers alive across a context switch. Fixes panics seen
on MP kernels.

ok drahn@

Change tb_freq to uint64_t. This prevents an overflow in the riscv64
implementation of delay(9).

ok deraadt@

When we do a context switch, always set the FPU to "off" for the old proc.
Disable the optimization to mark the new proc "clean" since it causes
random failures in regress. Hopefully we can revisit this soon.

ok drahn@

Add support for sfuart(4) as a console.

ok drahn@

Significant overhaul of the floating point save/restore code.
At this point the mechanism should closely resemble the powerpc64
save/restore points with one difference. (reload avoidance)
The previous 'aggressive' fpu save code that was (mostly) implemented before
and is present on arm32 and arm64.

There is one piece from that other design that remains, if
pcb->pcb_fpcpu == ci && ci->ci_fpuproc == p
after sleep, this will automatically re-activate the FPU state without
needing to reload it.
To enable this, the pointer pair is not changed on FPU context save
to indicate that the CPU still holds the valid content as long as both
of those pointers are pointing to each other.
Note that if another core steals the FPU conxtex (when we get to SMP)
the pcb->pcb_fpcpu will be another cpu, and from that it will know
to reload the FPU context. Also optimistically enabling this only makes
sense on riscv64 because there is the notion of FPU on and clean. Other
implimentations would need to 'fault on' the FPU enable, but could avoid
the FPU context load if no other processor has run this FPU context and no
other process has use FPU on this core.

ok kettenis@ deraadt@ Prior to a couple of fixes.

Get rid of the do-nothing cache setup code. The RISC-V architecture has
no architecturally defined caches (yet) so there is nothing to set up here.
Gets rid of some more useless XXX.

Sync memreg_add() implementation with arm64 and powerpc64.

remove uneeded includes

Use intr_enable()/int_disable()/intr_restore() instead of
enable_interrupts()/disable_interrupts()/restore_interrupts() and remove
the latter interfaces.

ok mlarkin@, drahn@

add OpenBSD rcs ids

more whitespace cleanups

whitespace cleanup

The clock on RISC-V is architectural, so we really don't need the
whole abstraction layer to support multiple timers. And we don't
really need a separate driver. Replace timer(4) with code based on
the powerpc64 implementation of the randomized statclock code.

Fixes hangs seen on real hardware.

ok jsg@, drahn@

Check that fdt hart id matches boot hart id before associating an fdt
node with the primary cpu.

Prompted by the polarfire icicle where hart 0 is an mmuless e51 core.

ok drahn@ mlarkin@

Use the EFI memory map (if available) to determine available physical
memory. This brings the code closer to arm64 but some key differences
remain. The most notable difference is that the riscv64 currently uses
its own private direct map of physical memory. Therefore it needs to know
the RAM address range which we derive from the /memory node in the FDT.

The code also needs to work around some bugs/flaws in the firmware:

* Newer OpenSBI versions no longer add a "no-map" property to the
reserved memory block that covers the memory used by OpenSBI itself.
This makes it appear as EfiBootServicesData in the EFI memory map,
which means it is available for general use.

* The OpenSBI shipped with the beaglev prototype boards doesn't reserve
the memory used by OpenBSI at all.

The workaround for the first issue is to remove all reserved memory blocks
specified in the FDT. In its current implementation this may remove
too much memory on certain boards.

The workaround for the second issue is to remove 2MB before the memory
where the kernel lives. This workaround is fragile since it relies on
a specific memory layout. Hopefully the beaglev firmware gets fixed and
we can remove this hack.

ok jsg@

change some commented vfp paths to riscv64 fpu equivalents

ok mlarkin@

Initialize the per-CPU pointer register early.

ok drahn@

fix logic error in boot()
ok deraadt@

Implement early console functionality based on available SBI calls.

While these calls are part of the legacy extensions and deprecated, they
are really useful for debugging purposes.

ok jsg@

reduce diff to current arm64

ok mlarkin@

remove commented arm console init lines

spelling

Initial import of OpenBSD/riscv64

This work is based on the effort:
https://www.openbsd.org/papers/Porting_OpenBSD_to_RISCV_FinalReport.pdf
"Porting OpenBSD to RISC-V ISA"
by
Brian Bamsch <bbamsch@google.com>
Wenyan He <wenyan.he@sjsu.edu>
Mars Li <mengshi.li.mars@gmail.com>
Shivam Waghela <shivamwaghela@gmail.com>

With additional work by Dale Rahn <drahn@openbsd.org>

The devicetree standard allows for multiple /memory nodes, each with
multiple memory ranges. We support the latter, but not the former.
Fix this, such that we detect all the memory on the Milk-V Pioneer
board.

ok miod@

revert r1.35

i dont know what i'm doing wrong with the handling of the no-map
property, but i'll find some coffee and time and figure it out soon
hopefully.

handle /reserved-memory nodes from device trees on arm64.

u-boot is supposed to take these entries and put them in the efi
memory map, but i keep hitting machines where an otherwise functional
u-boot does not do this, resulting in weird errors.

i have an espressobin with a vendor u-boot that has a reserved-memory
region for psci. without this diff the machine faults when the
kernel tries to reboot using a psci handler.

a macchiatobin with an otherwise working u-boot throws SErrors or
panics on weird memory corruption problems without this. i thought
it was bad RAM, but the problems persisted with completely different
ram, and very underclocked and well cooled ram.

riscv64 already has code to handle reserved-memory regions. the
riscv64 change is to add handling for the "no-map" property.

ok kettenis@

T-Head implemented a page attribute extension that violates the RISC-V
specification. The default attributes result in memory being uncached
which makes the system perform like a slug. So implement a workaround
that is designed to make implementation of the Svpbmt extension that is
part of the latest published RISC-V specification. This gets us a bit
further booting OpenBSD on an Allwinner D1 SoC.

ok mlarkin@, jca@

Account for nkmempages as well in the pmap_growkernel() call during
initalisation. This way there is enough KVA mapped that kmeminit()
succeeds even with large nkmempages. This is similar to e.g. alpha.
OK miod@ kettenis@

Skip leading dash in kernel boot options instead of complaining it is an
unknown option character.

cpu_idle_{enter,leave} are no-ops on riscv64, so just #define
away the calls

ok jca@

Print SBI vendor, version and implemented spec version

On my Unmatched:

SBI: OpenSBI v0.9, SBI Specification Version 0.2

ok mlarkin@

Simplfity setregs() by passing it the ps_strings and switching
sys_execve() to return EJUSTRETURN.

setregs() is the MD routine used by sys_execve() to set up the
thread's trapframe and PCB such that, on 'return' to userspace, it
has the register values defined by the ABI and otherwise zero. It
had to set the syscall retval[] values previously because the normal
syscall return path overwrites a couple registers with the retval[]
values. By instead returning EJUSTRETURN that and some complexity
with program-counter handling on m88k and sparc64 goes away.

Also, give setregs() add a 'struct ps_strings *arginfo' argument
so powerpc, powerpc64, and sh can directly get argc/argv/envp
values for registers instead of copyin()ing the one in userspace.

Improvements from miod@ and millert@
Testing assistance miod@, kettenis@, and aoyama@
ok miod@ kettenis@

Reorganize the EFI code a bit. Move the efi.h header from dev/acpi to
dev/efi and rename the arm64 efi.c to efi_machdep.c, preparing the way
for MI EFI code and an amd64 implementation of EFI runtime support.

ok deraadt@, mlarkin@

Do not bother initializing a0 with a special value in setregs, that's a
FreeBSDism we have no need for.
ok jsg@

Provide instruction cache invalidation through sysarch(RISCV_ICACHE_SYNC)

Modelled after the arm implementation. The first consumer would be
__builtin___clear_cache() in libcompiler_rt.

Input from kettenis@ and deraadt@, ok kettenis@

Remove a few pointless comments.

Cleanup early bootstrap code. This mostly realigns the code with the
FreeBSD code from which it was derived. In particular, it uses the same
trick to switch page tables as FreeBSD, which is what we use to spin up
the secondary CPUs already. This avoids having to install a temporary
1:1 mapping.

ok mlarkin@

Simplify the way we track the FPU state, using powerpc64 as a model.
The new code still uses the clean/dirty state that the hardware reports
to optimize saving/restoring the FPU register, but no longer attempts to
keep the FPU registers alive across a context switch. Fixes panics seen
on MP kernels.

ok drahn@

Change tb_freq to uint64_t. This prevents an overflow in the riscv64
implementation of delay(9).

ok deraadt@

When we do a context switch, always set the FPU to "off" for the old proc.
Disable the optimization to mark the new proc "clean" since it causes
random failures in regress. Hopefully we can revisit this soon.

ok drahn@

Add support for sfuart(4) as a console.

ok drahn@

Significant overhaul of the floating point save/restore code.
At this point the mechanism should closely resemble the powerpc64
save/restore points with one difference. (reload avoidance)
The previous 'aggressive' fpu save code that was (mostly) implemented before
and is present on arm32 and arm64.

There is one piece from that other design that remains, if
pcb->pcb_fpcpu == ci && ci->ci_fpuproc == p
after sleep, this will automatically re-activate the FPU state without
needing to reload it.
To enable this, the pointer pair is not changed on FPU context save
to indicate that the CPU still holds the valid content as long as both
of those pointers are pointing to each other.
Note that if another core steals the FPU conxtex (when we get to SMP)
the pcb->pcb_fpcpu will be another cpu, and from that it will know
to reload the FPU context. Also optimistically enabling this only makes
sense on riscv64 because there is the notion of FPU on and clean. Other
implimentations would need to 'fault on' the FPU enable, but could avoid
the FPU context load if no other processor has run this FPU context and no
other process has use FPU on this core.

ok kettenis@ deraadt@ Prior to a couple of fixes.

Get rid of the do-nothing cache setup code. The RISC-V architecture has
no architecturally defined caches (yet) so there is nothing to set up here.
Gets rid of some more useless XXX.

Sync memreg_add() implementation with arm64 and powerpc64.

remove uneeded includes

Use intr_enable()/int_disable()/intr_restore() instead of
enable_interrupts()/disable_interrupts()/restore_interrupts() and remove
the latter interfaces.

ok mlarkin@, drahn@

add OpenBSD rcs ids

more whitespace cleanups

whitespace cleanup

The clock on RISC-V is architectural, so we really don't need the
whole abstraction layer to support multiple timers. And we don't
really need a separate driver. Replace timer(4) with code based on
the powerpc64 implementation of the randomized statclock code.

Fixes hangs seen on real hardware.

ok jsg@, drahn@

Check that fdt hart id matches boot hart id before associating an fdt
node with the primary cpu.

Prompted by the polarfire icicle where hart 0 is an mmuless e51 core.

ok drahn@ mlarkin@

Use the EFI memory map (if available) to determine available physical
memory. This brings the code closer to arm64 but some key differences
remain. The most notable difference is that the riscv64 currently uses
its own private direct map of physical memory. Therefore it needs to know
the RAM address range which we derive from the /memory node in the FDT.

The code also needs to work around some bugs/flaws in the firmware:

* Newer OpenSBI versions no longer add a "no-map" property to the
reserved memory block that covers the memory used by OpenSBI itself.
This makes it appear as EfiBootServicesData in the EFI memory map,
which means it is available for general use.

* The OpenSBI shipped with the beaglev prototype boards doesn't reserve
the memory used by OpenBSI at all.

The workaround for the first issue is to remove all reserved memory blocks
specified in the FDT. In its current implementation this may remove
too much memory on certain boards.

The workaround for the second issue is to remove 2MB before the memory
where the kernel lives. This workaround is fragile since it relies on
a specific memory layout. Hopefully the beaglev firmware gets fixed and
we can remove this hack.

ok jsg@

change some commented vfp paths to riscv64 fpu equivalents

ok mlarkin@

Initialize the per-CPU pointer register early.

ok drahn@

fix logic error in boot()
ok deraadt@

Implement early console functionality based on available SBI calls.

While these calls are part of the legacy extensions and deprecated, they
are really useful for debugging purposes.

ok jsg@

reduce diff to current arm64

ok mlarkin@

remove commented arm console init lines

spelling

Initial import of OpenBSD/riscv64

This work is based on the effort:
https://www.openbsd.org/papers/Porting_OpenBSD_to_RISCV_FinalReport.pdf
"Porting OpenBSD to RISC-V ISA"
by
Brian Bamsch <bbamsch@google.com>
Wenyan He <wenyan.he@sjsu.edu>
Mars Li <mengshi.li.mars@gmail.com>
Shivam Waghela <shivamwaghela@gmail.com>

With additional work by Dale Rahn <drahn@openbsd.org>

revert r1.35

i dont know what i'm doing wrong with the handling of the no-map
property, but i'll find some coffee and time and figure it out soon
hopefully.

handle /reserved-memory nodes from device trees on arm64.

u-boot is supposed to take these entries and put them in the efi
memory map, but i keep hitting machines where an otherwise functional
u-boot does not do this, resulting in weird errors.

i have an espressobin with a vendor u-boot that has a reserved-memory
region for psci. without this diff the machine faults when the
kernel tries to reboot using a psci handler.

a macchiatobin with an otherwise working u-boot throws SErrors or
panics on weird memory corruption problems without this. i thought
it was bad RAM, but the problems persisted with completely different
ram, and very underclocked and well cooled ram.

riscv64 already has code to handle reserved-memory regions. the
riscv64 change is to add handling for the "no-map" property.

ok kettenis@

T-Head implemented a page attribute extension that violates the RISC-V
specification. The default attributes result in memory being uncached
which makes the system perform like a slug. So implement a workaround
that is designed to make implementation of the Svpbmt extension that is
part of the latest published RISC-V specification. This gets us a bit
further booting OpenBSD on an Allwinner D1 SoC.

ok mlarkin@, jca@

Account for nkmempages as well in the pmap_growkernel() call during
initalisation. This way there is enough KVA mapped that kmeminit()
succeeds even with large nkmempages. This is similar to e.g. alpha.
OK miod@ kettenis@

Skip leading dash in kernel boot options instead of complaining it is an
unknown option character.

cpu_idle_{enter,leave} are no-ops on riscv64, so just #define
away the calls

ok jca@

Print SBI vendor, version and implemented spec version

On my Unmatched:

SBI: OpenSBI v0.9, SBI Specification Version 0.2

ok mlarkin@

Simplfity setregs() by passing it the ps_strings and switching
sys_execve() to return EJUSTRETURN.

setregs() is the MD routine used by sys_execve() to set up the
thread's trapframe and PCB such that, on 'return' to userspace, it
has the register values defined by the ABI and otherwise zero. It
had to set the syscall retval[] values previously because the normal
syscall return path overwrites a couple registers with the retval[]
values. By instead returning EJUSTRETURN that and some complexity
with program-counter handling on m88k and sparc64 goes away.

Also, give setregs() add a 'struct ps_strings *arginfo' argument
so powerpc, powerpc64, and sh can directly get argc/argv/envp
values for registers instead of copyin()ing the one in userspace.

Improvements from miod@ and millert@
Testing assistance miod@, kettenis@, and aoyama@
ok miod@ kettenis@

Reorganize the EFI code a bit. Move the efi.h header from dev/acpi to
dev/efi and rename the arm64 efi.c to efi_machdep.c, preparing the way
for MI EFI code and an amd64 implementation of EFI runtime support.

ok deraadt@, mlarkin@

Do not bother initializing a0 with a special value in setregs, that's a
FreeBSDism we have no need for.
ok jsg@

Provide instruction cache invalidation through sysarch(RISCV_ICACHE_SYNC)

Modelled after the arm implementation. The first consumer would be
__builtin___clear_cache() in libcompiler_rt.

Input from kettenis@ and deraadt@, ok kettenis@

Remove a few pointless comments.

Cleanup early bootstrap code. This mostly realigns the code with the
FreeBSD code from which it was derived. In particular, it uses the same
trick to switch page tables as FreeBSD, which is what we use to spin up
the secondary CPUs already. This avoids having to install a temporary
1:1 mapping.

ok mlarkin@

Simplify the way we track the FPU state, using powerpc64 as a model.
The new code still uses the clean/dirty state that the hardware reports
to optimize saving/restoring the FPU register, but no longer attempts to
keep the FPU registers alive across a context switch. Fixes panics seen
on MP kernels.

ok drahn@

Change tb_freq to uint64_t. This prevents an overflow in the riscv64
implementation of delay(9).

ok deraadt@

When we do a context switch, always set the FPU to "off" for the old proc.
Disable the optimization to mark the new proc "clean" since it causes
random failures in regress. Hopefully we can revisit this soon.

ok drahn@

Add support for sfuart(4) as a console.

ok drahn@

Significant overhaul of the floating point save/restore code.
At this point the mechanism should closely resemble the powerpc64
save/restore points with one difference. (reload avoidance)
The previous 'aggressive' fpu save code that was (mostly) implemented before
and is present on arm32 and arm64.

There is one piece from that other design that remains, if
pcb->pcb_fpcpu == ci && ci->ci_fpuproc == p
after sleep, this will automatically re-activate the FPU state without
needing to reload it.
To enable this, the pointer pair is not changed on FPU context save
to indicate that the CPU still holds the valid content as long as both
of those pointers are pointing to each other.
Note that if another core steals the FPU conxtex (when we get to SMP)
the pcb->pcb_fpcpu will be another cpu, and from that it will know
to reload the FPU context. Also optimistically enabling this only makes
sense on riscv64 because there is the notion of FPU on and clean. Other
implimentations would need to 'fault on' the FPU enable, but could avoid
the FPU context load if no other processor has run this FPU context and no
other process has use FPU on this core.

ok kettenis@ deraadt@ Prior to a couple of fixes.

Get rid of the do-nothing cache setup code. The RISC-V architecture has
no architecturally defined caches (yet) so there is nothing to set up here.
Gets rid of some more useless XXX.

Sync memreg_add() implementation with arm64 and powerpc64.

remove uneeded includes

Use intr_enable()/int_disable()/intr_restore() instead of
enable_interrupts()/disable_interrupts()/restore_interrupts() and remove
the latter interfaces.

ok mlarkin@, drahn@

add OpenBSD rcs ids

more whitespace cleanups

whitespace cleanup

The clock on RISC-V is architectural, so we really don't need the
whole abstraction layer to support multiple timers. And we don't
really need a separate driver. Replace timer(4) with code based on
the powerpc64 implementation of the randomized statclock code.

Fixes hangs seen on real hardware.

ok jsg@, drahn@

Check that fdt hart id matches boot hart id before associating an fdt
node with the primary cpu.

Prompted by the polarfire icicle where hart 0 is an mmuless e51 core.

ok drahn@ mlarkin@

Use the EFI memory map (if available) to determine available physical
memory. This brings the code closer to arm64 but some key differences
remain. The most notable difference is that the riscv64 currently uses
its own private direct map of physical memory. Therefore it needs to know
the RAM address range which we derive from the /memory node in the FDT.

The code also needs to work around some bugs/flaws in the firmware:

* Newer OpenSBI versions no longer add a "no-map" property to the
reserved memory block that covers the memory used by OpenSBI itself.
This makes it appear as EfiBootServicesData in the EFI memory map,
which means it is available for general use.

* The OpenSBI shipped with the beaglev prototype boards doesn't reserve
the memory used by OpenBSI at all.

The workaround for the first issue is to remove all reserved memory blocks
specified in the FDT. In its current implementation this may remove
too much memory on certain boards.

The workaround for the second issue is to remove 2MB before the memory
where the kernel lives. This workaround is fragile since it relies on
a specific memory layout. Hopefully the beaglev firmware gets fixed and
we can remove this hack.

ok jsg@

change some commented vfp paths to riscv64 fpu equivalents

ok mlarkin@

Initialize the per-CPU pointer register early.

ok drahn@

fix logic error in boot()
ok deraadt@

Implement early console functionality based on available SBI calls.

While these calls are part of the legacy extensions and deprecated, they
are really useful for debugging purposes.

ok jsg@

reduce diff to current arm64

ok mlarkin@

remove commented arm console init lines

spelling

Initial import of OpenBSD/riscv64

This work is based on the effort:
https://www.openbsd.org/papers/Porting_OpenBSD_to_RISCV_FinalReport.pdf
"Porting OpenBSD to RISC-V ISA"
by
Brian Bamsch <bbamsch@google.com>
Wenyan He <wenyan.he@sjsu.edu>
Mars Li <mengshi.li.mars@gmail.com>
Shivam Waghela <shivamwaghela@gmail.com>

With additional work by Dale Rahn <drahn@openbsd.org>

T-Head implemented a page attribute extension that violates the RISC-V
specification. The default attributes result in memory being uncached
which makes the system perform like a slug. So implement a workaround
that is designed to make implementation of the Svpbmt extension that is
part of the latest published RISC-V specification. This gets us a bit
further booting OpenBSD on an Allwinner D1 SoC.

ok mlarkin@, jca@

Account for nkmempages as well in the pmap_growkernel() call during
initalisation. This way there is enough KVA mapped that kmeminit()
succeeds even with large nkmempages. This is similar to e.g. alpha.
OK miod@ kettenis@

Skip leading dash in kernel boot options instead of complaining it is an
unknown option character.

cpu_idle_{enter,leave} are no-ops on riscv64, so just #define
away the calls

ok jca@

Print SBI vendor, version and implemented spec version

On my Unmatched:

SBI: OpenSBI v0.9, SBI Specification Version 0.2

ok mlarkin@

Simplfity setregs() by passing it the ps_strings and switching
sys_execve() to return EJUSTRETURN.

setregs() is the MD routine used by sys_execve() to set up the
thread's trapframe and PCB such that, on 'return' to userspace, it
has the register values defined by the ABI and otherwise zero. It
had to set the syscall retval[] values previously because the normal
syscall return path overwrites a couple registers with the retval[]
values. By instead returning EJUSTRETURN that and some complexity
with program-counter handling on m88k and sparc64 goes away.

Also, give setregs() add a 'struct ps_strings *arginfo' argument
so powerpc, powerpc64, and sh can directly get argc/argv/envp
values for registers instead of copyin()ing the one in userspace.

Improvements from miod@ and millert@
Testing assistance miod@, kettenis@, and aoyama@
ok miod@ kettenis@

Reorganize the EFI code a bit. Move the efi.h header from dev/acpi to
dev/efi and rename the arm64 efi.c to efi_machdep.c, preparing the way
for MI EFI code and an amd64 implementation of EFI runtime support.

ok deraadt@, mlarkin@

Do not bother initializing a0 with a special value in setregs, that's a
FreeBSDism we have no need for.
ok jsg@

Provide instruction cache invalidation through sysarch(RISCV_ICACHE_SYNC)

Modelled after the arm implementation. The first consumer would be
__builtin___clear_cache() in libcompiler_rt.

Input from kettenis@ and deraadt@, ok kettenis@

Remove a few pointless comments.

Cleanup early bootstrap code. This mostly realigns the code with the
FreeBSD code from which it was derived. In particular, it uses the same
trick to switch page tables as FreeBSD, which is what we use to spin up
the secondary CPUs already. This avoids having to install a temporary
1:1 mapping.

ok mlarkin@

Simplify the way we track the FPU state, using powerpc64 as a model.
The new code still uses the clean/dirty state that the hardware reports
to optimize saving/restoring the FPU register, but no longer attempts to
keep the FPU registers alive across a context switch. Fixes panics seen
on MP kernels.

ok drahn@

Change tb_freq to uint64_t. This prevents an overflow in the riscv64
implementation of delay(9).

ok deraadt@

When we do a context switch, always set the FPU to "off" for the old proc.
Disable the optimization to mark the new proc "clean" since it causes
random failures in regress. Hopefully we can revisit this soon.

ok drahn@

Add support for sfuart(4) as a console.

ok drahn@

Significant overhaul of the floating point save/restore code.
At this point the mechanism should closely resemble the powerpc64
save/restore points with one difference. (reload avoidance)
The previous 'aggressive' fpu save code that was (mostly) implemented before
and is present on arm32 and arm64.

There is one piece from that other design that remains, if
pcb->pcb_fpcpu == ci && ci->ci_fpuproc == p
after sleep, this will automatically re-activate the FPU state without
needing to reload it.
To enable this, the pointer pair is not changed on FPU context save
to indicate that the CPU still holds the valid content as long as both
of those pointers are pointing to each other.
Note that if another core steals the FPU conxtex (when we get to SMP)
the pcb->pcb_fpcpu will be another cpu, and from that it will know
to reload the FPU context. Also optimistically enabling this only makes
sense on riscv64 because there is the notion of FPU on and clean. Other
implimentations would need to 'fault on' the FPU enable, but could avoid
the FPU context load if no other processor has run this FPU context and no
other process has use FPU on this core.

ok kettenis@ deraadt@ Prior to a couple of fixes.

Get rid of the do-nothing cache setup code. The RISC-V architecture has
no architecturally defined caches (yet) so there is nothing to set up here.
Gets rid of some more useless XXX.

Sync memreg_add() implementation with arm64 and powerpc64.

remove uneeded includes

Use intr_enable()/int_disable()/intr_restore() instead of
enable_interrupts()/disable_interrupts()/restore_interrupts() and remove
the latter interfaces.

ok mlarkin@, drahn@

add OpenBSD rcs ids

more whitespace cleanups

whitespace cleanup

The clock on RISC-V is architectural, so we really don't need the
whole abstraction layer to support multiple timers. And we don't
really need a separate driver. Replace timer(4) with code based on
the powerpc64 implementation of the randomized statclock code.

Fixes hangs seen on real hardware.

ok jsg@, drahn@

Check that fdt hart id matches boot hart id before associating an fdt
node with the primary cpu.

Prompted by the polarfire icicle where hart 0 is an mmuless e51 core.

ok drahn@ mlarkin@

Use the EFI memory map (if available) to determine available physical
memory. This brings the code closer to arm64 but some key differences
remain. The most notable difference is that the riscv64 currently uses
its own private direct map of physical memory. Therefore it needs to know
the RAM address range which we derive from the /memory node in the FDT.

The code also needs to work around some bugs/flaws in the firmware:

* Newer OpenSBI versions no longer add a "no-map" property to the
reserved memory block that covers the memory used by OpenSBI itself.
This makes it appear as EfiBootServicesData in the EFI memory map,
which means it is available for general use.

* The OpenSBI shipped with the beaglev prototype boards doesn't reserve
the memory used by OpenBSI at all.

The workaround for the first issue is to remove all reserved memory blocks
specified in the FDT. In its current implementation this may remove
too much memory on certain boards.

The workaround for the second issue is to remove 2MB before the memory
where the kernel lives. This workaround is fragile since it relies on
a specific memory layout. Hopefully the beaglev firmware gets fixed and
we can remove this hack.

ok jsg@

change some commented vfp paths to riscv64 fpu equivalents

ok mlarkin@

Initialize the per-CPU pointer register early.

ok drahn@

fix logic error in boot()
ok deraadt@

Implement early console functionality based on available SBI calls.

While these calls are part of the legacy extensions and deprecated, they
are really useful for debugging purposes.

ok jsg@

reduce diff to current arm64

ok mlarkin@

remove commented arm console init lines

spelling

Initial import of OpenBSD/riscv64

This work is based on the effort:
https://www.openbsd.org/papers/Porting_OpenBSD_to_RISCV_FinalReport.pdf
"Porting OpenBSD to RISC-V ISA"
by
Brian Bamsch <bbamsch@google.com>
Wenyan He <wenyan.he@sjsu.edu>
Mars Li <mengshi.li.mars@gmail.com>
Shivam Waghela <shivamwaghela@gmail.com>

With additional work by Dale Rahn <drahn@openbsd.org>

Account for nkmempages as well in the pmap_growkernel() call during
initalisation. This way there is enough KVA mapped that kmeminit()
succeeds even with large nkmempages. This is similar to e.g. alpha.
OK miod@ kettenis@

Skip leading dash in kernel boot options instead of complaining it is an
unknown option character.

cpu_idle_{enter,leave} are no-ops on riscv64, so just #define
away the calls

ok jca@

Print SBI vendor, version and implemented spec version

On my Unmatched:

SBI: OpenSBI v0.9, SBI Specification Version 0.2

ok mlarkin@

Simplfity setregs() by passing it the ps_strings and switching
sys_execve() to return EJUSTRETURN.

setregs() is the MD routine used by sys_execve() to set up the
thread's trapframe and PCB such that, on 'return' to userspace, it
has the register values defined by the ABI and otherwise zero. It
had to set the syscall retval[] values previously because the normal
syscall return path overwrites a couple registers with the retval[]
values. By instead returning EJUSTRETURN that and some complexity
with program-counter handling on m88k and sparc64 goes away.

Also, give setregs() add a 'struct ps_strings *arginfo' argument
so powerpc, powerpc64, and sh can directly get argc/argv/envp
values for registers instead of copyin()ing the one in userspace.

Improvements from miod@ and millert@
Testing assistance miod@, kettenis@, and aoyama@
ok miod@ kettenis@

Reorganize the EFI code a bit. Move the efi.h header from dev/acpi to
dev/efi and rename the arm64 efi.c to efi_machdep.c, preparing the way
for MI EFI code and an amd64 implementation of EFI runtime support.

ok deraadt@, mlarkin@

Do not bother initializing a0 with a special value in setregs, that's a
FreeBSDism we have no need for.
ok jsg@

Provide instruction cache invalidation through sysarch(RISCV_ICACHE_SYNC)

Modelled after the arm implementation. The first consumer would be
__builtin___clear_cache() in libcompiler_rt.

Input from kettenis@ and deraadt@, ok kettenis@

Remove a few pointless comments.

Cleanup early bootstrap code. This mostly realigns the code with the
FreeBSD code from which it was derived. In particular, it uses the same
trick to switch page tables as FreeBSD, which is what we use to spin up
the secondary CPUs already. This avoids having to install a temporary
1:1 mapping.

ok mlarkin@

Simplify the way we track the FPU state, using powerpc64 as a model.
The new code still uses the clean/dirty state that the hardware reports
to optimize saving/restoring the FPU register, but no longer attempts to
keep the FPU registers alive across a context switch. Fixes panics seen
on MP kernels.

ok drahn@

Change tb_freq to uint64_t. This prevents an overflow in the riscv64
implementation of delay(9).

ok deraadt@

When we do a context switch, always set the FPU to "off" for the old proc.
Disable the optimization to mark the new proc "clean" since it causes
random failures in regress. Hopefully we can revisit this soon.

ok drahn@

Add support for sfuart(4) as a console.

ok drahn@

Significant overhaul of the floating point save/restore code.
At this point the mechanism should closely resemble the powerpc64
save/restore points with one difference. (reload avoidance)
The previous 'aggressive' fpu save code that was (mostly) implemented before
and is present on arm32 and arm64.

There is one piece from that other design that remains, if
pcb->pcb_fpcpu == ci && ci->ci_fpuproc == p
after sleep, this will automatically re-activate the FPU state without
needing to reload it.
To enable this, the pointer pair is not changed on FPU context save
to indicate that the CPU still holds the valid content as long as both
of those pointers are pointing to each other.
Note that if another core steals the FPU conxtex (when we get to SMP)
the pcb->pcb_fpcpu will be another cpu, and from that it will know
to reload the FPU context. Also optimistically enabling this only makes
sense on riscv64 because there is the notion of FPU on and clean. Other
implimentations would need to 'fault on' the FPU enable, but could avoid
the FPU context load if no other processor has run this FPU context and no
other process has use FPU on this core.

ok kettenis@ deraadt@ Prior to a couple of fixes.

Get rid of the do-nothing cache setup code. The RISC-V architecture has
no architecturally defined caches (yet) so there is nothing to set up here.
Gets rid of some more useless XXX.

Sync memreg_add() implementation with arm64 and powerpc64.

remove uneeded includes

Use intr_enable()/int_disable()/intr_restore() instead of
enable_interrupts()/disable_interrupts()/restore_interrupts() and remove
the latter interfaces.

ok mlarkin@, drahn@

add OpenBSD rcs ids

more whitespace cleanups

whitespace cleanup

The clock on RISC-V is architectural, so we really don't need the
whole abstraction layer to support multiple timers. And we don't
really need a separate driver. Replace timer(4) with code based on
the powerpc64 implementation of the randomized statclock code.

Fixes hangs seen on real hardware.

ok jsg@, drahn@

Check that fdt hart id matches boot hart id before associating an fdt
node with the primary cpu.

Prompted by the polarfire icicle where hart 0 is an mmuless e51 core.

ok drahn@ mlarkin@

Use the EFI memory map (if available) to determine available physical
memory. This brings the code closer to arm64 but some key differences
remain. The most notable difference is that the riscv64 currently uses
its own private direct map of physical memory. Therefore it needs to know
the RAM address range which we derive from the /memory node in the FDT.

The code also needs to work around some bugs/flaws in the firmware:

* Newer OpenSBI versions no longer add a "no-map" property to the
reserved memory block that covers the memory used by OpenSBI itself.
This makes it appear as EfiBootServicesData in the EFI memory map,
which means it is available for general use.

* The OpenSBI shipped with the beaglev prototype boards doesn't reserve
the memory used by OpenBSI at all.

The workaround for the first issue is to remove all reserved memory blocks
specified in the FDT. In its current implementation this may remove
too much memory on certain boards.

The workaround for the second issue is to remove 2MB before the memory
where the kernel lives. This workaround is fragile since it relies on
a specific memory layout. Hopefully the beaglev firmware gets fixed and
we can remove this hack.

ok jsg@

change some commented vfp paths to riscv64 fpu equivalents

ok mlarkin@

Initialize the per-CPU pointer register early.

ok drahn@

fix logic error in boot()
ok deraadt@

Implement early console functionality based on available SBI calls.

While these calls are part of the legacy extensions and deprecated, they
are really useful for debugging purposes.

ok jsg@

reduce diff to current arm64

ok mlarkin@

remove commented arm console init lines

spelling

Initial import of OpenBSD/riscv64

This work is based on the effort:
https://www.openbsd.org/papers/Porting_OpenBSD_to_RISCV_FinalReport.pdf
"Porting OpenBSD to RISC-V ISA"
by
Brian Bamsch <bbamsch@google.com>
Wenyan He <wenyan.he@sjsu.edu>
Mars Li <mengshi.li.mars@gmail.com>
Shivam Waghela <shivamwaghela@gmail.com>

With additional work by Dale Rahn <drahn@openbsd.org>

Skip leading dash in kernel boot options instead of complaining it is an
unknown option character.

cpu_idle_{enter,leave} are no-ops on riscv64, so just #define
away the calls

ok jca@

Print SBI vendor, version and implemented spec version

On my Unmatched:

SBI: OpenSBI v0.9, SBI Specification Version 0.2

ok mlarkin@

Simplfity setregs() by passing it the ps_strings and switching
sys_execve() to return EJUSTRETURN.

setregs() is the MD routine used by sys_execve() to set up the
thread's trapframe and PCB such that, on 'return' to userspace, it
has the register values defined by the ABI and otherwise zero. It
had to set the syscall retval[] values previously because the normal
syscall return path overwrites a couple registers with the retval[]
values. By instead returning EJUSTRETURN that and some complexity
with program-counter handling on m88k and sparc64 goes away.

Also, give setregs() add a 'struct ps_strings *arginfo' argument
so powerpc, powerpc64, and sh can directly get argc/argv/envp
values for registers instead of copyin()ing the one in userspace.

Improvements from miod@ and millert@
Testing assistance miod@, kettenis@, and aoyama@
ok miod@ kettenis@

Reorganize the EFI code a bit. Move the efi.h header from dev/acpi to
dev/efi and rename the arm64 efi.c to efi_machdep.c, preparing the way
for MI EFI code and an amd64 implementation of EFI runtime support.

ok deraadt@, mlarkin@

Do not bother initializing a0 with a special value in setregs, that's a
FreeBSDism we have no need for.
ok jsg@

Provide instruction cache invalidation through sysarch(RISCV_ICACHE_SYNC)

Modelled after the arm implementation. The first consumer would be
__builtin___clear_cache() in libcompiler_rt.

Input from kettenis@ and deraadt@, ok kettenis@

Remove a few pointless comments.

Cleanup early bootstrap code. This mostly realigns the code with the
FreeBSD code from which it was derived. In particular, it uses the same
trick to switch page tables as FreeBSD, which is what we use to spin up
the secondary CPUs already. This avoids having to install a temporary
1:1 mapping.

ok mlarkin@

Simplify the way we track the FPU state, using powerpc64 as a model.
The new code still uses the clean/dirty state that the hardware reports
to optimize saving/restoring the FPU register, but no longer attempts to
keep the FPU registers alive across a context switch. Fixes panics seen
on MP kernels.

ok drahn@

Change tb_freq to uint64_t. This prevents an overflow in the riscv64
implementation of delay(9).

ok deraadt@

When we do a context switch, always set the FPU to "off" for the old proc.
Disable the optimization to mark the new proc "clean" since it causes
random failures in regress. Hopefully we can revisit this soon.

ok drahn@

Add support for sfuart(4) as a console.

ok drahn@

Significant overhaul of the floating point save/restore code.
At this point the mechanism should closely resemble the powerpc64
save/restore points with one difference. (reload avoidance)
The previous 'aggressive' fpu save code that was (mostly) implemented before
and is present on arm32 and arm64.

There is one piece from that other design that remains, if
pcb->pcb_fpcpu == ci && ci->ci_fpuproc == p
after sleep, this will automatically re-activate the FPU state without
needing to reload it.
To enable this, the pointer pair is not changed on FPU context save
to indicate that the CPU still holds the valid content as long as both
of those pointers are pointing to each other.
Note that if another core steals the FPU conxtex (when we get to SMP)
the pcb->pcb_fpcpu will be another cpu, and from that it will know
to reload the FPU context. Also optimistically enabling this only makes
sense on riscv64 because there is the notion of FPU on and clean. Other
implimentations would need to 'fault on' the FPU enable, but could avoid
the FPU context load if no other processor has run this FPU context and no
other process has use FPU on this core.

ok kettenis@ deraadt@ Prior to a couple of fixes.

Get rid of the do-nothing cache setup code. The RISC-V architecture has
no architecturally defined caches (yet) so there is nothing to set up here.
Gets rid of some more useless XXX.

Sync memreg_add() implementation with arm64 and powerpc64.

remove uneeded includes

Use intr_enable()/int_disable()/intr_restore() instead of
enable_interrupts()/disable_interrupts()/restore_interrupts() and remove
the latter interfaces.

ok mlarkin@, drahn@

add OpenBSD rcs ids

more whitespace cleanups

whitespace cleanup

The clock on RISC-V is architectural, so we really don't need the
whole abstraction layer to support multiple timers. And we don't
really need a separate driver. Replace timer(4) with code based on
the powerpc64 implementation of the randomized statclock code.

Fixes hangs seen on real hardware.

ok jsg@, drahn@

Check that fdt hart id matches boot hart id before associating an fdt
node with the primary cpu.

Prompted by the polarfire icicle where hart 0 is an mmuless e51 core.

ok drahn@ mlarkin@

Use the EFI memory map (if available) to determine available physical
memory. This brings the code closer to arm64 but some key differences
remain. The most notable difference is that the riscv64 currently uses
its own private direct map of physical memory. Therefore it needs to know
the RAM address range which we derive from the /memory node in the FDT.

The code also needs to work around some bugs/flaws in the firmware:

* Newer OpenSBI versions no longer add a "no-map" property to the
reserved memory block that covers the memory used by OpenSBI itself.
This makes it appear as EfiBootServicesData in the EFI memory map,
which means it is available for general use.

* The OpenSBI shipped with the beaglev prototype boards doesn't reserve
the memory used by OpenBSI at all.

The workaround for the first issue is to remove all reserved memory blocks
specified in the FDT. In its current implementation this may remove
too much memory on certain boards.

The workaround for the second issue is to remove 2MB before the memory
where the kernel lives. This workaround is fragile since it relies on
a specific memory layout. Hopefully the beaglev firmware gets fixed and
we can remove this hack.

ok jsg@

change some commented vfp paths to riscv64 fpu equivalents

ok mlarkin@

Initialize the per-CPU pointer register early.

ok drahn@

fix logic error in boot()
ok deraadt@

Implement early console functionality based on available SBI calls.

While these calls are part of the legacy extensions and deprecated, they
are really useful for debugging purposes.

ok jsg@

reduce diff to current arm64

ok mlarkin@

remove commented arm console init lines

spelling

Initial import of OpenBSD/riscv64

This work is based on the effort:
https://www.openbsd.org/papers/Porting_OpenBSD_to_RISCV_FinalReport.pdf
"Porting OpenBSD to RISC-V ISA"
by
Brian Bamsch <bbamsch@google.com>
Wenyan He <wenyan.he@sjsu.edu>
Mars Li <mengshi.li.mars@gmail.com>
Shivam Waghela <shivamwaghela@gmail.com>

With additional work by Dale Rahn <drahn@openbsd.org>

cpu_idle_{enter,leave} are no-ops on riscv64, so just #define
away the calls

ok jca@

Print SBI vendor, version and implemented spec version

On my Unmatched:

SBI: OpenSBI v0.9, SBI Specification Version 0.2

ok mlarkin@

Simplfity setregs() by passing it the ps_strings and switching
sys_execve() to return EJUSTRETURN.

setregs() is the MD routine used by sys_execve() to set up the
thread's trapframe and PCB such that, on 'return' to userspace, it
has the register values defined by the ABI and otherwise zero. It
had to set the syscall retval[] values previously because the normal
syscall return path overwrites a couple registers with the retval[]
values. By instead returning EJUSTRETURN that and some complexity
with program-counter handling on m88k and sparc64 goes away.

Also, give setregs() add a 'struct ps_strings *arginfo' argument
so powerpc, powerpc64, and sh can directly get argc/argv/envp
values for registers instead of copyin()ing the one in userspace.

Improvements from miod@ and millert@
Testing assistance miod@, kettenis@, and aoyama@
ok miod@ kettenis@

Reorganize the EFI code a bit. Move the efi.h header from dev/acpi to
dev/efi and rename the arm64 efi.c to efi_machdep.c, preparing the way
for MI EFI code and an amd64 implementation of EFI runtime support.

ok deraadt@, mlarkin@

Do not bother initializing a0 with a special value in setregs, that's a
FreeBSDism we have no need for.
ok jsg@

Provide instruction cache invalidation through sysarch(RISCV_ICACHE_SYNC)

Modelled after the arm implementation. The first consumer would be
__builtin___clear_cache() in libcompiler_rt.

Input from kettenis@ and deraadt@, ok kettenis@

Remove a few pointless comments.

Cleanup early bootstrap code. This mostly realigns the code with the
FreeBSD code from which it was derived. In particular, it uses the same
trick to switch page tables as FreeBSD, which is what we use to spin up
the secondary CPUs already. This avoids having to install a temporary
1:1 mapping.

ok mlarkin@

Simplify the way we track the FPU state, using powerpc64 as a model.
The new code still uses the clean/dirty state that the hardware reports
to optimize saving/restoring the FPU register, but no longer attempts to
keep the FPU registers alive across a context switch. Fixes panics seen
on MP kernels.

ok drahn@

Change tb_freq to uint64_t. This prevents an overflow in the riscv64
implementation of delay(9).

ok deraadt@

When we do a context switch, always set the FPU to "off" for the old proc.
Disable the optimization to mark the new proc "clean" since it causes
random failures in regress. Hopefully we can revisit this soon.

ok drahn@

Add support for sfuart(4) as a console.

ok drahn@

Significant overhaul of the floating point save/restore code.
At this point the mechanism should closely resemble the powerpc64
save/restore points with one difference. (reload avoidance)
The previous 'aggressive' fpu save code that was (mostly) implemented before
and is present on arm32 and arm64.

There is one piece from that other design that remains, if
pcb->pcb_fpcpu == ci && ci->ci_fpuproc == p
after sleep, this will automatically re-activate the FPU state without
needing to reload it.
To enable this, the pointer pair is not changed on FPU context save
to indicate that the CPU still holds the valid content as long as both
of those pointers are pointing to each other.
Note that if another core steals the FPU conxtex (when we get to SMP)
the pcb->pcb_fpcpu will be another cpu, and from that it will know
to reload the FPU context. Also optimistically enabling this only makes
sense on riscv64 because there is the notion of FPU on and clean. Other
implimentations would need to 'fault on' the FPU enable, but could avoid
the FPU context load if no other processor has run this FPU context and no
other process has use FPU on this core.

ok kettenis@ deraadt@ Prior to a couple of fixes.

Get rid of the do-nothing cache setup code. The RISC-V architecture has
no architecturally defined caches (yet) so there is nothing to set up here.
Gets rid of some more useless XXX.

Sync memreg_add() implementation with arm64 and powerpc64.

remove uneeded includes

Use intr_enable()/int_disable()/intr_restore() instead of
enable_interrupts()/disable_interrupts()/restore_interrupts() and remove
the latter interfaces.

ok mlarkin@, drahn@

add OpenBSD rcs ids

more whitespace cleanups

whitespace cleanup

The clock on RISC-V is architectural, so we really don't need the
whole abstraction layer to support multiple timers. And we don't
really need a separate driver. Replace timer(4) with code based on
the powerpc64 implementation of the randomized statclock code.

Fixes hangs seen on real hardware.

ok jsg@, drahn@

Check that fdt hart id matches boot hart id before associating an fdt
node with the primary cpu.

Prompted by the polarfire icicle where hart 0 is an mmuless e51 core.

ok drahn@ mlarkin@

Use the EFI memory map (if available) to determine available physical
memory. This brings the code closer to arm64 but some key differences
remain. The most notable difference is that the riscv64 currently uses
its own private direct map of physical memory. Therefore it needs to know
the RAM address range which we derive from the /memory node in the FDT.

The code also needs to work around some bugs/flaws in the firmware:

* Newer OpenSBI versions no longer add a "no-map" property to the
reserved memory block that covers the memory used by OpenSBI itself.
This makes it appear as EfiBootServicesData in the EFI memory map,
which means it is available for general use.

* The OpenSBI shipped with the beaglev prototype boards doesn't reserve
the memory used by OpenBSI at all.

The workaround for the first issue is to remove all reserved memory blocks
specified in the FDT. In its current implementation this may remove
too much memory on certain boards.

The workaround for the second issue is to remove 2MB before the memory
where the kernel lives. This workaround is fragile since it relies on
a specific memory layout. Hopefully the beaglev firmware gets fixed and
we can remove this hack.

ok jsg@

change some commented vfp paths to riscv64 fpu equivalents

ok mlarkin@

Initialize the per-CPU pointer register early.

ok drahn@

fix logic error in boot()
ok deraadt@

Implement early console functionality based on available SBI calls.

While these calls are part of the legacy extensions and deprecated, they
are really useful for debugging purposes.

ok jsg@

reduce diff to current arm64

ok mlarkin@

remove commented arm console init lines

spelling

Initial import of OpenBSD/riscv64

This work is based on the effort:
https://www.openbsd.org/papers/Porting_OpenBSD_to_RISCV_FinalReport.pdf
"Porting OpenBSD to RISC-V ISA"
by
Brian Bamsch <bbamsch@google.com>
Wenyan He <wenyan.he@sjsu.edu>
Mars Li <mengshi.li.mars@gmail.com>
Shivam Waghela <shivamwaghela@gmail.com>

With additional work by Dale Rahn <drahn@openbsd.org>

Print SBI vendor, version and implemented spec version

On my Unmatched:

SBI: OpenSBI v0.9, SBI Specification Version 0.2

ok mlarkin@

Simplfity setregs() by passing it the ps_strings and switching
sys_execve() to return EJUSTRETURN.

setregs() is the MD routine used by sys_execve() to set up the
thread's trapframe and PCB such that, on 'return' to userspace, it
has the register values defined by the ABI and otherwise zero. It
had to set the syscall retval[] values previously because the normal
syscall return path overwrites a couple registers with the retval[]
values. By instead returning EJUSTRETURN that and some complexity
with program-counter handling on m88k and sparc64 goes away.

Also, give setregs() add a 'struct ps_strings *arginfo' argument
so powerpc, powerpc64, and sh can directly get argc/argv/envp
values for registers instead of copyin()ing the one in userspace.

Improvements from miod@ and millert@
Testing assistance miod@, kettenis@, and aoyama@
ok miod@ kettenis@

Reorganize the EFI code a bit. Move the efi.h header from dev/acpi to
dev/efi and rename the arm64 efi.c to efi_machdep.c, preparing the way
for MI EFI code and an amd64 implementation of EFI runtime support.

ok deraadt@, mlarkin@

Do not bother initializing a0 with a special value in setregs, that's a
FreeBSDism we have no need for.
ok jsg@

Provide instruction cache invalidation through sysarch(RISCV_ICACHE_SYNC)

Modelled after the arm implementation. The first consumer would be
__builtin___clear_cache() in libcompiler_rt.

Input from kettenis@ and deraadt@, ok kettenis@

Remove a few pointless comments.

Cleanup early bootstrap code. This mostly realigns the code with the
FreeBSD code from which it was derived. In particular, it uses the same
trick to switch page tables as FreeBSD, which is what we use to spin up
the secondary CPUs already. This avoids having to install a temporary
1:1 mapping.

ok mlarkin@

Simplify the way we track the FPU state, using powerpc64 as a model.
The new code still uses the clean/dirty state that the hardware reports
to optimize saving/restoring the FPU register, but no longer attempts to
keep the FPU registers alive across a context switch. Fixes panics seen
on MP kernels.

ok drahn@

Change tb_freq to uint64_t. This prevents an overflow in the riscv64
implementation of delay(9).

ok deraadt@

When we do a context switch, always set the FPU to "off" for the old proc.
Disable the optimization to mark the new proc "clean" since it causes
random failures in regress. Hopefully we can revisit this soon.

ok drahn@

Add support for sfuart(4) as a console.

ok drahn@

Significant overhaul of the floating point save/restore code.
At this point the mechanism should closely resemble the powerpc64
save/restore points with one difference. (reload avoidance)
The previous 'aggressive' fpu save code that was (mostly) implemented before
and is present on arm32 and arm64.

There is one piece from that other design that remains, if
pcb->pcb_fpcpu == ci && ci->ci_fpuproc == p
after sleep, this will automatically re-activate the FPU state without
needing to reload it.
To enable this, the pointer pair is not changed on FPU context save
to indicate that the CPU still holds the valid content as long as both
of those pointers are pointing to each other.
Note that if another core steals the FPU conxtex (when we get to SMP)
the pcb->pcb_fpcpu will be another cpu, and from that it will know
to reload the FPU context. Also optimistically enabling this only makes
sense on riscv64 because there is the notion of FPU on and clean. Other
implimentations would need to 'fault on' the FPU enable, but could avoid
the FPU context load if no other processor has run this FPU context and no
other process has use FPU on this core.

ok kettenis@ deraadt@ Prior to a couple of fixes.

Get rid of the do-nothing cache setup code. The RISC-V architecture has
no architecturally defined caches (yet) so there is nothing to set up here.
Gets rid of some more useless XXX.

Sync memreg_add() implementation with arm64 and powerpc64.

remove uneeded includes

Use intr_enable()/int_disable()/intr_restore() instead of
enable_interrupts()/disable_interrupts()/restore_interrupts() and remove
the latter interfaces.

ok mlarkin@, drahn@

add OpenBSD rcs ids

more whitespace cleanups

whitespace cleanup

The clock on RISC-V is architectural, so we really don't need the
whole abstraction layer to support multiple timers. And we don't
really need a separate driver. Replace timer(4) with code based on
the powerpc64 implementation of the randomized statclock code.

Fixes hangs seen on real hardware.

ok jsg@, drahn@

Check that fdt hart id matches boot hart id before associating an fdt
node with the primary cpu.

Prompted by the polarfire icicle where hart 0 is an mmuless e51 core.

ok drahn@ mlarkin@

Use the EFI memory map (if available) to determine available physical
memory. This brings the code closer to arm64 but some key differences
remain. The most notable difference is that the riscv64 currently uses
its own private direct map of physical memory. Therefore it needs to know
the RAM address range which we derive from the /memory node in the FDT.

The code also needs to work around some bugs/flaws in the firmware:

* Newer OpenSBI versions no longer add a "no-map" property to the
reserved memory block that covers the memory used by OpenSBI itself.
This makes it appear as EfiBootServicesData in the EFI memory map,
which means it is available for general use.

* The OpenSBI shipped with the beaglev prototype boards doesn't reserve
the memory used by OpenBSI at all.

The workaround for the first issue is to remove all reserved memory blocks
specified in the FDT. In its current implementation this may remove
too much memory on certain boards.

The workaround for the second issue is to remove 2MB before the memory
where the kernel lives. This workaround is fragile since it relies on
a specific memory layout. Hopefully the beaglev firmware gets fixed and
we can remove this hack.

ok jsg@

change some commented vfp paths to riscv64 fpu equivalents

ok mlarkin@

Initialize the per-CPU pointer register early.

ok drahn@

fix logic error in boot()
ok deraadt@

Implement early console functionality based on available SBI calls.

While these calls are part of the legacy extensions and deprecated, they
are really useful for debugging purposes.

ok jsg@

reduce diff to current arm64

ok mlarkin@

remove commented arm console init lines

spelling

Initial import of OpenBSD/riscv64

This work is based on the effort:
https://www.openbsd.org/papers/Porting_OpenBSD_to_RISCV_FinalReport.pdf
"Porting OpenBSD to RISC-V ISA"
by
Brian Bamsch <bbamsch@google.com>
Wenyan He <wenyan.he@sjsu.edu>
Mars Li <mengshi.li.mars@gmail.com>
Shivam Waghela <shivamwaghela@gmail.com>

With additional work by Dale Rahn <drahn@openbsd.org>

Simplfity setregs() by passing it the ps_strings and switching
sys_execve() to return EJUSTRETURN.

setregs() is the MD routine used by sys_execve() to set up the
thread's trapframe and PCB such that, on 'return' to userspace, it
has the register values defined by the ABI and otherwise zero. It
had to set the syscall retval[] values previously because the normal
syscall return path overwrites a couple registers with the retval[]
values. By instead returning EJUSTRETURN that and some complexity
with program-counter handling on m88k and sparc64 goes away.

Also, give setregs() add a 'struct ps_strings *arginfo' argument
so powerpc, powerpc64, and sh can directly get argc/argv/envp
values for registers instead of copyin()ing the one in userspace.

Improvements from miod@ and millert@
Testing assistance miod@, kettenis@, and aoyama@
ok miod@ kettenis@

Reorganize the EFI code a bit. Move the efi.h header from dev/acpi to
dev/efi and rename the arm64 efi.c to efi_machdep.c, preparing the way
for MI EFI code and an amd64 implementation of EFI runtime support.

ok deraadt@, mlarkin@

Do not bother initializing a0 with a special value in setregs, that's a
FreeBSDism we have no need for.
ok jsg@

Provide instruction cache invalidation through sysarch(RISCV_ICACHE_SYNC)

Modelled after the arm implementation. The first consumer would be
__builtin___clear_cache() in libcompiler_rt.

Input from kettenis@ and deraadt@, ok kettenis@

Remove a few pointless comments.

Cleanup early bootstrap code. This mostly realigns the code with the
FreeBSD code from which it was derived. In particular, it uses the same
trick to switch page tables as FreeBSD, which is what we use to spin up
the secondary CPUs already. This avoids having to install a temporary
1:1 mapping.

ok mlarkin@

Simplify the way we track the FPU state, using powerpc64 as a model.
The new code still uses the clean/dirty state that the hardware reports
to optimize saving/restoring the FPU register, but no longer attempts to
keep the FPU registers alive across a context switch. Fixes panics seen
on MP kernels.

ok drahn@

Change tb_freq to uint64_t. This prevents an overflow in the riscv64
implementation of delay(9).

ok deraadt@

When we do a context switch, always set the FPU to "off" for the old proc.
Disable the optimization to mark the new proc "clean" since it causes
random failures in regress. Hopefully we can revisit this soon.

ok drahn@

Add support for sfuart(4) as a console.

ok drahn@

Significant overhaul of the floating point save/restore code.
At this point the mechanism should closely resemble the powerpc64
save/restore points with one difference. (reload avoidance)
The previous 'aggressive' fpu save code that was (mostly) implemented before
and is present on arm32 and arm64.

There is one piece from that other design that remains, if
pcb->pcb_fpcpu == ci && ci->ci_fpuproc == p
after sleep, this will automatically re-activate the FPU state without
needing to reload it.
To enable this, the pointer pair is not changed on FPU context save
to indicate that the CPU still holds the valid content as long as both
of those pointers are pointing to each other.
Note that if another core steals the FPU conxtex (when we get to SMP)
the pcb->pcb_fpcpu will be another cpu, and from that it will know
to reload the FPU context. Also optimistically enabling this only makes
sense on riscv64 because there is the notion of FPU on and clean. Other
implimentations would need to 'fault on' the FPU enable, but could avoid
the FPU context load if no other processor has run this FPU context and no
other process has use FPU on this core.

ok kettenis@ deraadt@ Prior to a couple of fixes.

Get rid of the do-nothing cache setup code. The RISC-V architecture has
no architecturally defined caches (yet) so there is nothing to set up here.
Gets rid of some more useless XXX.

Sync memreg_add() implementation with arm64 and powerpc64.

remove uneeded includes

Use intr_enable()/int_disable()/intr_restore() instead of
enable_interrupts()/disable_interrupts()/restore_interrupts() and remove
the latter interfaces.

ok mlarkin@, drahn@

add OpenBSD rcs ids

more whitespace cleanups

whitespace cleanup

The clock on RISC-V is architectural, so we really don't need the
whole abstraction layer to support multiple timers. And we don't
really need a separate driver. Replace timer(4) with code based on
the powerpc64 implementation of the randomized statclock code.

Fixes hangs seen on real hardware.

ok jsg@, drahn@

Check that fdt hart id matches boot hart id before associating an fdt
node with the primary cpu.

Prompted by the polarfire icicle where hart 0 is an mmuless e51 core.

ok drahn@ mlarkin@

Use the EFI memory map (if available) to determine available physical
memory. This brings the code closer to arm64 but some key differences
remain. The most notable difference is that the riscv64 currently uses
its own private direct map of physical memory. Therefore it needs to know
the RAM address range which we derive from the /memory node in the FDT.

The code also needs to work around some bugs/flaws in the firmware:

* Newer OpenSBI versions no longer add a "no-map" property to the
reserved memory block that covers the memory used by OpenSBI itself.
This makes it appear as EfiBootServicesData in the EFI memory map,
which means it is available for general use.

* The OpenSBI shipped with the beaglev prototype boards doesn't reserve
the memory used by OpenBSI at all.

The workaround for the first issue is to remove all reserved memory blocks
specified in the FDT. In its current implementation this may remove
too much memory on certain boards.

The workaround for the second issue is to remove 2MB before the memory
where the kernel lives. This workaround is fragile since it relies on
a specific memory layout. Hopefully the beaglev firmware gets fixed and
we can remove this hack.

ok jsg@

change some commented vfp paths to riscv64 fpu equivalents

ok mlarkin@

Initialize the per-CPU pointer register early.

ok drahn@

fix logic error in boot()
ok deraadt@

Implement early console functionality based on available SBI calls.

While these calls are part of the legacy extensions and deprecated, they
are really useful for debugging purposes.

ok jsg@

reduce diff to current arm64

ok mlarkin@

remove commented arm console init lines

spelling

Initial import of OpenBSD/riscv64

This work is based on the effort:
https://www.openbsd.org/papers/Porting_OpenBSD_to_RISCV_FinalReport.pdf
"Porting OpenBSD to RISC-V ISA"
by
Brian Bamsch <bbamsch@google.com>
Wenyan He <wenyan.he@sjsu.edu>
Mars Li <mengshi.li.mars@gmail.com>
Shivam Waghela <shivamwaghela@gmail.com>

With additional work by Dale Rahn <drahn@openbsd.org>

Reorganize the EFI code a bit. Move the efi.h header from dev/acpi to
dev/efi and rename the arm64 efi.c to efi_machdep.c, preparing the way
for MI EFI code and an amd64 implementation of EFI runtime support.

ok deraadt@, mlarkin@

Do not bother initializing a0 with a special value in setregs, that's a
FreeBSDism we have no need for.
ok jsg@

Provide instruction cache invalidation through sysarch(RISCV_ICACHE_SYNC)

Modelled after the arm implementation. The first consumer would be
__builtin___clear_cache() in libcompiler_rt.

Input from kettenis@ and deraadt@, ok kettenis@

Remove a few pointless comments.

Cleanup early bootstrap code. This mostly realigns the code with the
FreeBSD code from which it was derived. In particular, it uses the same
trick to switch page tables as FreeBSD, which is what we use to spin up
the secondary CPUs already. This avoids having to install a temporary
1:1 mapping.

ok mlarkin@

Simplify the way we track the FPU state, using powerpc64 as a model.
The new code still uses the clean/dirty state that the hardware reports
to optimize saving/restoring the FPU register, but no longer attempts to
keep the FPU registers alive across a context switch. Fixes panics seen
on MP kernels.

ok drahn@

Change tb_freq to uint64_t. This prevents an overflow in the riscv64
implementation of delay(9).

ok deraadt@

When we do a context switch, always set the FPU to "off" for the old proc.
Disable the optimization to mark the new proc "clean" since it causes
random failures in regress. Hopefully we can revisit this soon.

ok drahn@

Add support for sfuart(4) as a console.

ok drahn@

Significant overhaul of the floating point save/restore code.
At this point the mechanism should closely resemble the powerpc64
save/restore points with one difference. (reload avoidance)
The previous 'aggressive' fpu save code that was (mostly) implemented before
and is present on arm32 and arm64.

There is one piece from that other design that remains, if
pcb->pcb_fpcpu == ci && ci->ci_fpuproc == p
after sleep, this will automatically re-activate the FPU state without
needing to reload it.
To enable this, the pointer pair is not changed on FPU context save
to indicate that the CPU still holds the valid content as long as both
of those pointers are pointing to each other.
Note that if another core steals the FPU conxtex (when we get to SMP)
the pcb->pcb_fpcpu will be another cpu, and from that it will know
to reload the FPU context. Also optimistically enabling this only makes
sense on riscv64 because there is the notion of FPU on and clean. Other
implimentations would need to 'fault on' the FPU enable, but could avoid
the FPU context load if no other processor has run this FPU context and no
other process has use FPU on this core.

ok kettenis@ deraadt@ Prior to a couple of fixes.

Get rid of the do-nothing cache setup code. The RISC-V architecture has
no architecturally defined caches (yet) so there is nothing to set up here.
Gets rid of some more useless XXX.

Sync memreg_add() implementation with arm64 and powerpc64.

remove uneeded includes

Use intr_enable()/int_disable()/intr_restore() instead of
enable_interrupts()/disable_interrupts()/restore_interrupts() and remove
the latter interfaces.

ok mlarkin@, drahn@

add OpenBSD rcs ids

more whitespace cleanups

whitespace cleanup

The clock on RISC-V is architectural, so we really don't need the
whole abstraction layer to support multiple timers. And we don't
really need a separate driver. Replace timer(4) with code based on
the powerpc64 implementation of the randomized statclock code.

Fixes hangs seen on real hardware.

ok jsg@, drahn@

Check that fdt hart id matches boot hart id before associating an fdt
node with the primary cpu.

Prompted by the polarfire icicle where hart 0 is an mmuless e51 core.

ok drahn@ mlarkin@

Use the EFI memory map (if available) to determine available physical
memory. This brings the code closer to arm64 but some key differences
remain. The most notable difference is that the riscv64 currently uses
its own private direct map of physical memory. Therefore it needs to know
the RAM address range which we derive from the /memory node in the FDT.

The code also needs to work around some bugs/flaws in the firmware:

* Newer OpenSBI versions no longer add a "no-map" property to the
reserved memory block that covers the memory used by OpenSBI itself.
This makes it appear as EfiBootServicesData in the EFI memory map,
which means it is available for general use.

* The OpenSBI shipped with the beaglev prototype boards doesn't reserve
the memory used by OpenBSI at all.

The workaround for the first issue is to remove all reserved memory blocks
specified in the FDT. In its current implementation this may remove
too much memory on certain boards.

The workaround for the second issue is to remove 2MB before the memory
where the kernel lives. This workaround is fragile since it relies on
a specific memory layout. Hopefully the beaglev firmware gets fixed and
we can remove this hack.

ok jsg@

change some commented vfp paths to riscv64 fpu equivalents

ok mlarkin@

Initialize the per-CPU pointer register early.

ok drahn@

fix logic error in boot()
ok deraadt@

Implement early console functionality based on available SBI calls.

While these calls are part of the legacy extensions and deprecated, they
are really useful for debugging purposes.

ok jsg@

reduce diff to current arm64

ok mlarkin@

remove commented arm console init lines

spelling

Initial import of OpenBSD/riscv64

This work is based on the effort:
https://www.openbsd.org/papers/Porting_OpenBSD_to_RISCV_FinalReport.pdf
"Porting OpenBSD to RISC-V ISA"
by
Brian Bamsch <bbamsch@google.com>
Wenyan He <wenyan.he@sjsu.edu>
Mars Li <mengshi.li.mars@gmail.com>
Shivam Waghela <shivamwaghela@gmail.com>

With additional work by Dale Rahn <drahn@openbsd.org>

Do not bother initializing a0 with a special value in setregs, that's a
FreeBSDism we have no need for.
ok jsg@

Provide instruction cache invalidation through sysarch(RISCV_ICACHE_SYNC)

Modelled after the arm implementation. The first consumer would be
__builtin___clear_cache() in libcompiler_rt.

Input from kettenis@ and deraadt@, ok kettenis@

Remove a few pointless comments.

Cleanup early bootstrap code. This mostly realigns the code with the
FreeBSD code from which it was derived. In particular, it uses the same
trick to switch page tables as FreeBSD, which is what we use to spin up
the secondary CPUs already. This avoids having to install a temporary
1:1 mapping.

ok mlarkin@

Simplify the way we track the FPU state, using powerpc64 as a model.
The new code still uses the clean/dirty state that the hardware reports
to optimize saving/restoring the FPU register, but no longer attempts to
keep the FPU registers alive across a context switch. Fixes panics seen
on MP kernels.

ok drahn@

Change tb_freq to uint64_t. This prevents an overflow in the riscv64
implementation of delay(9).

ok deraadt@

When we do a context switch, always set the FPU to "off" for the old proc.
Disable the optimization to mark the new proc "clean" since it causes
random failures in regress. Hopefully we can revisit this soon.

ok drahn@

Add support for sfuart(4) as a console.

ok drahn@

Significant overhaul of the floating point save/restore code.
At this point the mechanism should closely resemble the powerpc64
save/restore points with one difference. (reload avoidance)
The previous 'aggressive' fpu save code that was (mostly) implemented before
and is present on arm32 and arm64.

There is one piece from that other design that remains, if
pcb->pcb_fpcpu == ci && ci->ci_fpuproc == p
after sleep, this will automatically re-activate the FPU state without
needing to reload it.
To enable this, the pointer pair is not changed on FPU context save
to indicate that the CPU still holds the valid content as long as both
of those pointers are pointing to each other.
Note that if another core steals the FPU conxtex (when we get to SMP)
the pcb->pcb_fpcpu will be another cpu, and from that it will know
to reload the FPU context. Also optimistically enabling this only makes
sense on riscv64 because there is the notion of FPU on and clean. Other
implimentations would need to 'fault on' the FPU enable, but could avoid
the FPU context load if no other processor has run this FPU context and no
other process has use FPU on this core.

ok kettenis@ deraadt@ Prior to a couple of fixes.

Get rid of the do-nothing cache setup code. The RISC-V architecture has
no architecturally defined caches (yet) so there is nothing to set up here.
Gets rid of some more useless XXX.

Sync memreg_add() implementation with arm64 and powerpc64.

remove uneeded includes

Use intr_enable()/int_disable()/intr_restore() instead of
enable_interrupts()/disable_interrupts()/restore_interrupts() and remove
the latter interfaces.

ok mlarkin@, drahn@

add OpenBSD rcs ids

more whitespace cleanups

whitespace cleanup

The clock on RISC-V is architectural, so we really don't need the
whole abstraction layer to support multiple timers. And we don't
really need a separate driver. Replace timer(4) with code based on
the powerpc64 implementation of the randomized statclock code.

Fixes hangs seen on real hardware.

ok jsg@, drahn@

Check that fdt hart id matches boot hart id before associating an fdt
node with the primary cpu.

Prompted by the polarfire icicle where hart 0 is an mmuless e51 core.

ok drahn@ mlarkin@

Use the EFI memory map (if available) to determine available physical
memory. This brings the code closer to arm64 but some key differences
remain. The most notable difference is that the riscv64 currently uses
its own private direct map of physical memory. Therefore it needs to know
the RAM address range which we derive from the /memory node in the FDT.

The code also needs to work around some bugs/flaws in the firmware:

* Newer OpenSBI versions no longer add a "no-map" property to the
reserved memory block that covers the memory used by OpenSBI itself.
This makes it appear as EfiBootServicesData in the EFI memory map,
which means it is available for general use.

* The OpenSBI shipped with the beaglev prototype boards doesn't reserve
the memory used by OpenBSI at all.

The workaround for the first issue is to remove all reserved memory blocks
specified in the FDT. In its current implementation this may remove
too much memory on certain boards.

The workaround for the second issue is to remove 2MB before the memory
where the kernel lives. This workaround is fragile since it relies on
a specific memory layout. Hopefully the beaglev firmware gets fixed and
we can remove this hack.

ok jsg@

change some commented vfp paths to riscv64 fpu equivalents

ok mlarkin@

Initialize the per-CPU pointer register early.

ok drahn@

fix logic error in boot()
ok deraadt@

Implement early console functionality based on available SBI calls.

While these calls are part of the legacy extensions and deprecated, they
are really useful for debugging purposes.

ok jsg@

reduce diff to current arm64

ok mlarkin@

remove commented arm console init lines

spelling

Initial import of OpenBSD/riscv64

This work is based on the effort:
https://www.openbsd.org/papers/Porting_OpenBSD_to_RISCV_FinalReport.pdf
"Porting OpenBSD to RISC-V ISA"
by
Brian Bamsch <bbamsch@google.com>
Wenyan He <wenyan.he@sjsu.edu>
Mars Li <mengshi.li.mars@gmail.com>
Shivam Waghela <shivamwaghela@gmail.com>

With additional work by Dale Rahn <drahn@openbsd.org>

Provide instruction cache invalidation through sysarch(RISCV_ICACHE_SYNC)

Modelled after the arm implementation. The first consumer would be
__builtin___clear_cache() in libcompiler_rt.

Input from kettenis@ and deraadt@, ok kettenis@

Remove a few pointless comments.

Cleanup early bootstrap code. This mostly realigns the code with the
FreeBSD code from which it was derived. In particular, it uses the same
trick to switch page tables as FreeBSD, which is what we use to spin up
the secondary CPUs already. This avoids having to install a temporary
1:1 mapping.

ok mlarkin@

Simplify the way we track the FPU state, using powerpc64 as a model.
The new code still uses the clean/dirty state that the hardware reports
to optimize saving/restoring the FPU register, but no longer attempts to
keep the FPU registers alive across a context switch. Fixes panics seen
on MP kernels.

ok drahn@

Change tb_freq to uint64_t. This prevents an overflow in the riscv64
implementation of delay(9).

ok deraadt@

When we do a context switch, always set the FPU to "off" for the old proc.
Disable the optimization to mark the new proc "clean" since it causes
random failures in regress. Hopefully we can revisit this soon.

ok drahn@

Add support for sfuart(4) as a console.

ok drahn@

Significant overhaul of the floating point save/restore code.
At this point the mechanism should closely resemble the powerpc64
save/restore points with one difference. (reload avoidance)
The previous 'aggressive' fpu save code that was (mostly) implemented before
and is present on arm32 and arm64.

There is one piece from that other design that remains, if
pcb->pcb_fpcpu == ci && ci->ci_fpuproc == p
after sleep, this will automatically re-activate the FPU state without
needing to reload it.
To enable this, the pointer pair is not changed on FPU context save
to indicate that the CPU still holds the valid content as long as both
of those pointers are pointing to each other.
Note that if another core steals the FPU conxtex (when we get to SMP)
the pcb->pcb_fpcpu will be another cpu, and from that it will know
to reload the FPU context. Also optimistically enabling this only makes
sense on riscv64 because there is the notion of FPU on and clean. Other
implimentations would need to 'fault on' the FPU enable, but could avoid
the FPU context load if no other processor has run this FPU context and no
other process has use FPU on this core.

ok kettenis@ deraadt@ Prior to a couple of fixes.

Get rid of the do-nothing cache setup code. The RISC-V architecture has
no architecturally defined caches (yet) so there is nothing to set up here.
Gets rid of some more useless XXX.

Sync memreg_add() implementation with arm64 and powerpc64.

remove uneeded includes

Use intr_enable()/int_disable()/intr_restore() instead of
enable_interrupts()/disable_interrupts()/restore_interrupts() and remove
the latter interfaces.

ok mlarkin@, drahn@

add OpenBSD rcs ids

more whitespace cleanups

whitespace cleanup

The clock on RISC-V is architectural, so we really don't need the
whole abstraction layer to support multiple timers. And we don't
really need a separate driver. Replace timer(4) with code based on
the powerpc64 implementation of the randomized statclock code.

Fixes hangs seen on real hardware.

ok jsg@, drahn@

Check that fdt hart id matches boot hart id before associating an fdt
node with the primary cpu.

Prompted by the polarfire icicle where hart 0 is an mmuless e51 core.

ok drahn@ mlarkin@

Use the EFI memory map (if available) to determine available physical
memory. This brings the code closer to arm64 but some key differences
remain. The most notable difference is that the riscv64 currently uses
its own private direct map of physical memory. Therefore it needs to know
the RAM address range which we derive from the /memory node in the FDT.

The code also needs to work around some bugs/flaws in the firmware:

* Newer OpenSBI versions no longer add a "no-map" property to the
reserved memory block that covers the memory used by OpenSBI itself.
This makes it appear as EfiBootServicesData in the EFI memory map,
which means it is available for general use.

* The OpenSBI shipped with the beaglev prototype boards doesn't reserve
the memory used by OpenBSI at all.

The workaround for the first issue is to remove all reserved memory blocks
specified in the FDT. In its current implementation this may remove
too much memory on certain boards.

The workaround for the second issue is to remove 2MB before the memory
where the kernel lives. This workaround is fragile since it relies on
a specific memory layout. Hopefully the beaglev firmware gets fixed and
we can remove this hack.

ok jsg@

change some commented vfp paths to riscv64 fpu equivalents

ok mlarkin@

Initialize the per-CPU pointer register early.

ok drahn@

fix logic error in boot()
ok deraadt@

Implement early console functionality based on available SBI calls.

While these calls are part of the legacy extensions and deprecated, they
are really useful for debugging purposes.

ok jsg@

reduce diff to current arm64

ok mlarkin@

remove commented arm console init lines

spelling

Initial import of OpenBSD/riscv64

This work is based on the effort:
https://www.openbsd.org/papers/Porting_OpenBSD_to_RISCV_FinalReport.pdf
"Porting OpenBSD to RISC-V ISA"
by
Brian Bamsch <bbamsch@google.com>
Wenyan He <wenyan.he@sjsu.edu>
Mars Li <mengshi.li.mars@gmail.com>
Shivam Waghela <shivamwaghela@gmail.com>

With additional work by Dale Rahn <drahn@openbsd.org>

Remove a few pointless comments.

Cleanup early bootstrap code. This mostly realigns the code with the
FreeBSD code from which it was derived. In particular, it uses the same
trick to switch page tables as FreeBSD, which is what we use to spin up
the secondary CPUs already. This avoids having to install a temporary
1:1 mapping.

ok mlarkin@

Simplify the way we track the FPU state, using powerpc64 as a model.
The new code still uses the clean/dirty state that the hardware reports
to optimize saving/restoring the FPU register, but no longer attempts to
keep the FPU registers alive across a context switch. Fixes panics seen
on MP kernels.

ok drahn@

Change tb_freq to uint64_t. This prevents an overflow in the riscv64
implementation of delay(9).

ok deraadt@

When we do a context switch, always set the FPU to "off" for the old proc.
Disable the optimization to mark the new proc "clean" since it causes
random failures in regress. Hopefully we can revisit this soon.

ok drahn@

Add support for sfuart(4) as a console.

ok drahn@

Significant overhaul of the floating point save/restore code.
At this point the mechanism should closely resemble the powerpc64
save/restore points with one difference. (reload avoidance)
The previous 'aggressive' fpu save code that was (mostly) implemented before
and is present on arm32 and arm64.

There is one piece from that other design that remains, if
pcb->pcb_fpcpu == ci && ci->ci_fpuproc == p
after sleep, this will automatically re-activate the FPU state without
needing to reload it.
To enable this, the pointer pair is not changed on FPU context save
to indicate that the CPU still holds the valid content as long as both
of those pointers are pointing to each other.
Note that if another core steals the FPU conxtex (when we get to SMP)
the pcb->pcb_fpcpu will be another cpu, and from that it will know
to reload the FPU context. Also optimistically enabling this only makes
sense on riscv64 because there is the notion of FPU on and clean. Other
implimentations would need to 'fault on' the FPU enable, but could avoid
the FPU context load if no other processor has run this FPU context and no
other process has use FPU on this core.

ok kettenis@ deraadt@ Prior to a couple of fixes.

Get rid of the do-nothing cache setup code. The RISC-V architecture has
no architecturally defined caches (yet) so there is nothing to set up here.
Gets rid of some more useless XXX.

Sync memreg_add() implementation with arm64 and powerpc64.

remove uneeded includes

Use intr_enable()/int_disable()/intr_restore() instead of
enable_interrupts()/disable_interrupts()/restore_interrupts() and remove
the latter interfaces.

ok mlarkin@, drahn@

add OpenBSD rcs ids

more whitespace cleanups

whitespace cleanup

The clock on RISC-V is architectural, so we really don't need the
whole abstraction layer to support multiple timers. And we don't
really need a separate driver. Replace timer(4) with code based on
the powerpc64 implementation of the randomized statclock code.

Fixes hangs seen on real hardware.

ok jsg@, drahn@

Check that fdt hart id matches boot hart id before associating an fdt
node with the primary cpu.

Prompted by the polarfire icicle where hart 0 is an mmuless e51 core.

ok drahn@ mlarkin@