| #
1.4 |
|
20-May-2021 |
drahn |
Significant overhaul of the floating point save/restore code.
At this point the mechanism should closely resemble the powerpc64
save/restore points with one difference. (reload avoidance)
The previous 'aggressive' fpu save code that was (mostly) implemented before
and is present on arm32 and arm64.
There is one piece from that other design that remains, if
pcb->pcb_fpcpu == ci && ci->ci_fpuproc == p
after sleep, this will automatically re-activate the FPU state without
needing to reload it.
To enable this, the pointer pair is not changed on FPU context save
to indicate that the CPU still holds the valid content as long as both
of those pointers are pointing to each other.
Note that if another core steals the FPU conxtex (when we get to SMP)
the pcb->pcb_fpcpu will be another cpu, and from that it will know
to reload the FPU context. Also optimistically enabling this only makes
sense on riscv64 because there is the notion of FPU on and clean. Other
implimentations would need to 'fault on' the FPU enable, but could avoid
the FPU context load if no other processor has run this FPU context and no
other process has use FPU on this core.
ok kettenis@ deraadt@ Prior to a couple of fixes.
(this file was missing from original commit)
|
| #
1.3 |
|
13-May-2021 |
jsg |
change sig_atomic_t from long to int matching all the other archs
ok kettenis@
|
| #
1.2 |
|
12-May-2021 |
jsg |
add OpenBSD rcs ids
|
| #
1.1 |
|
23-Apr-2021 |
drahn |
Initial import of OpenBSD/riscv64
This work is based on the effort:
https://www.openbsd.org/papers/Porting_OpenBSD_to_RISCV_FinalReport.pdf
"Porting OpenBSD to RISC-V ISA"
by
Brian Bamsch <bbamsch@google.com>
Wenyan He <wenyan.he@sjsu.edu>
Mars Li <mengshi.li.mars@gmail.com>
Shivam Waghela <shivamwaghela@gmail.com>
With additional work by Dale Rahn <drahn@openbsd.org>
|
| #
1.3 |
|
13-May-2021 |
jsg |
change sig_atomic_t from long to int matching all the other archs
ok kettenis@
|
| #
1.2 |
|
12-May-2021 |
jsg |
add OpenBSD rcs ids
|
| #
1.1 |
|
23-Apr-2021 |
drahn |
Initial import of OpenBSD/riscv64
This work is based on the effort:
https://www.openbsd.org/papers/Porting_OpenBSD_to_RISCV_FinalReport.pdf
"Porting OpenBSD to RISC-V ISA"
by
Brian Bamsch <bbamsch@google.com>
Wenyan He <wenyan.he@sjsu.edu>
Mars Li <mengshi.li.mars@gmail.com>
Shivam Waghela <shivamwaghela@gmail.com>
With additional work by Dale Rahn <drahn@openbsd.org>
|
| #
1.2 |
|
12-May-2021 |
jsg |
add OpenBSD rcs ids
|
| #
1.1 |
|
23-Apr-2021 |
drahn |
Initial import of OpenBSD/riscv64
This work is based on the effort:
https://www.openbsd.org/papers/Porting_OpenBSD_to_RISCV_FinalReport.pdf
"Porting OpenBSD to RISC-V ISA"
by
Brian Bamsch <bbamsch@google.com>
Wenyan He <wenyan.he@sjsu.edu>
Mars Li <mengshi.li.mars@gmail.com>
Shivam Waghela <shivamwaghela@gmail.com>
With additional work by Dale Rahn <drahn@openbsd.org>
|
| #
1.1 |
|
23-Apr-2021 |
drahn |
Initial import of OpenBSD/riscv64
This work is based on the effort:
https://www.openbsd.org/papers/Porting_OpenBSD_to_RISCV_FinalReport.pdf
"Porting OpenBSD to RISC-V ISA"
by
Brian Bamsch <bbamsch@google.com>
Wenyan He <wenyan.he@sjsu.edu>
Mars Li <mengshi.li.mars@gmail.com>
Shivam Waghela <shivamwaghela@gmail.com>
With additional work by Dale Rahn <drahn@openbsd.org>
|