Change len in syncicache(_, len) from int to size_t

The powerpc64 part is under #if 0, so this change affects only macppc.
Simplify powerpc64's __syncicache (which had size_t len) and copy it
to macppc's syncicache (which had int len).

macppc was looping while ((l -= CACHELINESIZE) > 0). The loop would
be infinite if l became an unsigned type like size_t. It is simpler
to set size_t i = 0, do i += by, and loop while (i < len). It helps
that dcbst and icbi can add 2 registers, from + i.

use ansi volatile keyword, not __volatile
ok miod@ guenther@

Use the right "virtual address" when flushing TLB entries.
Implement pmap_{is|clear}_{referenced|modified}.
Fix PTED_PTEGIDX().

Teach powerpc64 ddb to x, w, break, step, trace.

Copy and adapt db_memrw.c from amd64, so ddb can read and write kernel
memory. It can now insert breakpoints in the kernel text. Change
__syncicache() to prevent an infinite loop when len isn't a multiple
of cacheline_size.

Get breakpoints and single-stepping to work.
Single-stepping uses msr bit PSL_SE (single-step trace enable).

Adapt db_trace.c db_stack_trace_print() from powerpc 32, but without
all its features. For now, powerpc64 trace doesn't print function
arguments and doesn't recognize traps.

"go for it" kettenis@

Add some very simple trap handling.

use ansi volatile keyword, not __volatile
ok miod@ guenther@

Use the right "virtual address" when flushing TLB entries.
Implement pmap_{is|clear}_{referenced|modified}.
Fix PTED_PTEGIDX().

Teach powerpc64 ddb to x, w, break, step, trace.

Copy and adapt db_memrw.c from amd64, so ddb can read and write kernel
memory. It can now insert breakpoints in the kernel text. Change
__syncicache() to prevent an infinite loop when len isn't a multiple
of cacheline_size.

Get breakpoints and single-stepping to work.
Single-stepping uses msr bit PSL_SE (single-step trace enable).

Adapt db_trace.c db_stack_trace_print() from powerpc 32, but without
all its features. For now, powerpc64 trace doesn't print function
arguments and doesn't recognize traps.

"go for it" kettenis@

Add some very simple trap handling.

Use the right "virtual address" when flushing TLB entries.
Implement pmap_{is|clear}_{referenced|modified}.
Fix PTED_PTEGIDX().

Teach powerpc64 ddb to x, w, break, step, trace.

Copy and adapt db_memrw.c from amd64, so ddb can read and write kernel
memory. It can now insert breakpoints in the kernel text. Change
__syncicache() to prevent an infinite loop when len isn't a multiple
of cacheline_size.

Get breakpoints and single-stepping to work.
Single-stepping uses msr bit PSL_SE (single-step trace enable).

Adapt db_trace.c db_stack_trace_print() from powerpc 32, but without
all its features. For now, powerpc64 trace doesn't print function
arguments and doesn't recognize traps.

"go for it" kettenis@

Add some very simple trap handling.

Teach powerpc64 ddb to x, w, break, step, trace.

Copy and adapt db_memrw.c from amd64, so ddb can read and write kernel
memory. It can now insert breakpoints in the kernel text. Change
__syncicache() to prevent an infinite loop when len isn't a multiple
of cacheline_size.

Get breakpoints and single-stepping to work.
Single-stepping uses msr bit PSL_SE (single-step trace enable).

Adapt db_trace.c db_stack_trace_print() from powerpc 32, but without
all its features. For now, powerpc64 trace doesn't print function
arguments and doesn't recognize traps.

"go for it" kettenis@

Add some very simple trap handling.

Add some very simple trap handling.