#
1.5 |
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01-Sep-2019 |
visa |
Make it clearer where message "spurious interrupt" comes from.
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Revision tags: OPENBSD_6_5_BASE
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#
1.4 |
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17-Mar-2019 |
visa |
Let each interrupt controller driver choose how to implement intr_barrier(9).
With this change, the barrier should finally work properly with cnmac(4) interrupts that have been assigned to secondary cores.
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#
1.3 |
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16-Mar-2019 |
visa |
Include header <sys/evcount.h> where event counters are used, so that header <machine/intr.h> can eventually stop including it on octeon.
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Revision tags: OPENBSD_6_2_BASE OPENBSD_6_3_BASE OPENBSD_6_4_BASE
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#
1.2 |
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31-Jul-2017 |
visa |
Assume edge triggering by default for robustness, as is done in octcit(4).
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#
1.1 |
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13-Jul-2017 |
visa |
Add a driver for the CIB interrupt controller. Certain device controllers need it on CN70xx/CN71xx.
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#
1.4 |
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17-Mar-2019 |
visa |
Let each interrupt controller driver choose how to implement intr_barrier(9).
With this change, the barrier should finally work properly with cnmac(4) interrupts that have been assigned to secondary cores.
|
#
1.3 |
|
16-Mar-2019 |
visa |
Include header <sys/evcount.h> where event counters are used, so that header <machine/intr.h> can eventually stop including it on octeon.
|
Revision tags: OPENBSD_6_2_BASE OPENBSD_6_3_BASE OPENBSD_6_4_BASE
|
#
1.2 |
|
31-Jul-2017 |
visa |
Assume edge triggering by default for robustness, as is done in octcit(4).
|
#
1.1 |
|
13-Jul-2017 |
visa |
Add a driver for the CIB interrupt controller. Certain device controllers need it on CN70xx/CN71xx.
|
Revision tags: OPENBSD_6_2_BASE
|
#
1.2 |
|
31-Jul-2017 |
visa |
Assume edge triggering by default for robustness, as is done in octcit(4).
|
#
1.1 |
|
13-Jul-2017 |
visa |
Add a driver for the CIB interrupt controller. Certain device controllers need it on CN70xx/CN71xx.
|