spelling

Mask off IPL flags before storing the IPL for an interrupt.
This fixes the IPL calculations in mpic_calc_mask() in the presence
of IPL_MPSAFE interrupts such as mvneta(4).

ok patrick@ kettenis@ dlg@

Constify struct cfattach.

ok visa@ a long time ago, ok patrick@

Extend the interrupt API on arm64 and armv7 to be able to pass around
a struct cpu_info *. From a driver point of view the fdt_intr_establish_*
API now also exist same functions with a *_cpu suffix. Internally the
"old" functions now call their *_cpu counterparts, passing NULL as ci.
NULL will be interpreted as primary CPU in the interrupt controller code.

The internal framework for interrupt controllers has been changed so that
the establish methods provided by an interrupt controller function always
takes a struct cpu_info *.

Some drivers, like imxgpio(4) and rkgpio(4), only have a single interrupt
line for multiple pins. On those we simply disallow trying to establish
an interrupt on a non-primary CPU, returning NULL.

Since we do not have MP yet on armv7, all armv7 interrupt controllers do
return NULL if an attempt is made to establish an interrupt on a different
CPU. That said, so far there's no way this can happen. If we ever gain
MP support, this is a reminder that the interrupt controller drivers have
to be adjusted.

Prompted by dlg@
ok kettenis@

For shared interrupts we need to make sure that we register
with the lowest IPL. Once we actually run the IRQ handler
we raise to the highest IPL. Fixes a crash seen when having
a network card in the PCIe slot of the MacchiatoBin.

ok ccardenas@

Add missing OpenBSD CVS tag

Add mvmpic(4), a driver for the interrupt controller that sits between
the ARM Generic Interrupt Controller and the Ethernet controller on
the Armada 388 (SolidRun ClearFog, Turris Omnia).

ok kettenis@

Mask off IPL flags before storing the IPL for an interrupt.
This fixes the IPL calculations in mpic_calc_mask() in the presence
of IPL_MPSAFE interrupts such as mvneta(4).

ok patrick@ kettenis@ dlg@

Constify struct cfattach.

ok visa@ a long time ago, ok patrick@

Extend the interrupt API on arm64 and armv7 to be able to pass around
a struct cpu_info *. From a driver point of view the fdt_intr_establish_*
API now also exist same functions with a *_cpu suffix. Internally the
"old" functions now call their *_cpu counterparts, passing NULL as ci.
NULL will be interpreted as primary CPU in the interrupt controller code.

The internal framework for interrupt controllers has been changed so that
the establish methods provided by an interrupt controller function always
takes a struct cpu_info *.

Some drivers, like imxgpio(4) and rkgpio(4), only have a single interrupt
line for multiple pins. On those we simply disallow trying to establish
an interrupt on a non-primary CPU, returning NULL.

Since we do not have MP yet on armv7, all armv7 interrupt controllers do
return NULL if an attempt is made to establish an interrupt on a different
CPU. That said, so far there's no way this can happen. If we ever gain
MP support, this is a reminder that the interrupt controller drivers have
to be adjusted.

Prompted by dlg@
ok kettenis@

For shared interrupts we need to make sure that we register
with the lowest IPL. Once we actually run the IRQ handler
we raise to the highest IPL. Fixes a crash seen when having
a network card in the PCIe slot of the MacchiatoBin.

ok ccardenas@

Add missing OpenBSD CVS tag

Add mvmpic(4), a driver for the interrupt controller that sits between
the ARM Generic Interrupt Controller and the Ethernet controller on
the Armada 388 (SolidRun ClearFog, Turris Omnia).

ok kettenis@

Constify struct cfattach.

ok visa@ a long time ago, ok patrick@

Extend the interrupt API on arm64 and armv7 to be able to pass around
a struct cpu_info *. From a driver point of view the fdt_intr_establish_*
API now also exist same functions with a *_cpu suffix. Internally the
"old" functions now call their *_cpu counterparts, passing NULL as ci.
NULL will be interpreted as primary CPU in the interrupt controller code.

The internal framework for interrupt controllers has been changed so that
the establish methods provided by an interrupt controller function always
takes a struct cpu_info *.

Some drivers, like imxgpio(4) and rkgpio(4), only have a single interrupt
line for multiple pins. On those we simply disallow trying to establish
an interrupt on a non-primary CPU, returning NULL.

Since we do not have MP yet on armv7, all armv7 interrupt controllers do
return NULL if an attempt is made to establish an interrupt on a different
CPU. That said, so far there's no way this can happen. If we ever gain
MP support, this is a reminder that the interrupt controller drivers have
to be adjusted.

Prompted by dlg@
ok kettenis@

For shared interrupts we need to make sure that we register
with the lowest IPL. Once we actually run the IRQ handler
we raise to the highest IPL. Fixes a crash seen when having
a network card in the PCIe slot of the MacchiatoBin.

ok ccardenas@

Add missing OpenBSD CVS tag

Add mvmpic(4), a driver for the interrupt controller that sits between
the ARM Generic Interrupt Controller and the Ethernet controller on
the Armada 388 (SolidRun ClearFog, Turris Omnia).

ok kettenis@

Extend the interrupt API on arm64 and armv7 to be able to pass around
a struct cpu_info *. From a driver point of view the fdt_intr_establish_*
API now also exist same functions with a *_cpu suffix. Internally the
"old" functions now call their *_cpu counterparts, passing NULL as ci.
NULL will be interpreted as primary CPU in the interrupt controller code.

The internal framework for interrupt controllers has been changed so that
the establish methods provided by an interrupt controller function always
takes a struct cpu_info *.

Some drivers, like imxgpio(4) and rkgpio(4), only have a single interrupt
line for multiple pins. On those we simply disallow trying to establish
an interrupt on a non-primary CPU, returning NULL.

Since we do not have MP yet on armv7, all armv7 interrupt controllers do
return NULL if an attempt is made to establish an interrupt on a different
CPU. That said, so far there's no way this can happen. If we ever gain
MP support, this is a reminder that the interrupt controller drivers have
to be adjusted.

Prompted by dlg@
ok kettenis@

For shared interrupts we need to make sure that we register
with the lowest IPL. Once we actually run the IRQ handler
we raise to the highest IPL. Fixes a crash seen when having
a network card in the PCIe slot of the MacchiatoBin.

ok ccardenas@

Add missing OpenBSD CVS tag

Add mvmpic(4), a driver for the interrupt controller that sits between
the ARM Generic Interrupt Controller and the Ethernet controller on
the Armada 388 (SolidRun ClearFog, Turris Omnia).

ok kettenis@

For shared interrupts we need to make sure that we register
with the lowest IPL. Once we actually run the IRQ handler
we raise to the highest IPL. Fixes a crash seen when having
a network card in the PCIe slot of the MacchiatoBin.

ok ccardenas@

Add missing OpenBSD CVS tag

Add mvmpic(4), a driver for the interrupt controller that sits between
the ARM Generic Interrupt Controller and the Ethernet controller on
the Armada 388 (SolidRun ClearFog, Turris Omnia).

ok kettenis@

Add missing OpenBSD CVS tag

Add mvmpic(4), a driver for the interrupt controller that sits between
the ARM Generic Interrupt Controller and the Ethernet controller on
the Armada 388 (SolidRun ClearFog, Turris Omnia).

ok kettenis@