We don't do compat32 so MSR_CSTAR shouldn't be set up: delete the
Xsyscall32 stub and UCODE32 selector, set MSR_CSTAR to zero at CPU
startup, and rezero on ACPI resume and VM exit.

requested a while ago by deraadt@
AMD VM testing chris@
testing and ok krw@

Implement Multiple Message MSI support on amd64. This is experimental code
to assist qwx(4) development. We may remove this code again at some point
in the future.

Multiple Message MSI has some serious design flaws, especially when
combined with the APIC interrupt controller architecture. It was
superseded by MSI-X. Unfortunately qwx(4) does not implement MSI-X.

ok stsp@, deraadt@

Explicitly declare the gdt storage in struct cpu_info_full instead of
implicitly putting it in the padding to page-size. This eliminates a
couple Coverity issues from the Meltdown work.

testing daniel@
ok mlarkin@

How about I delete _all_ the BITFIELDTYPE comments?

lint is dead: BITFIELDTYPE comments aren't useful

ok miller@

LDT is gone and not coming back

Treat primary cpu like others and put pointer to its GDT in cpu_info.ci_gdt

requested by and ok mlarkin@

Normalize sentinel. Use _MACHINE_*_H_ and _<ARCH>_*_H_ properly and consitently.

Discussed and okay drahn@. Okay deraadt@.

__attribute__((packed)) -> __packed. The ioprbs.c chunk was commented out, and
uncommenting it is intentional.
ok deraadt@

Switch from TSS-per-process to TSS-per-CPU, placing the TSS right
next to the cpu's GDT, also making the double-fault stack per-CPU,
leaving it at the top of the page of the CPU's idle process. Inline
pmap_activate() and pmap_deactivate() into the asm cpu_switchto
routine, adding a check for the new pmap already being marked as
active on the CPU. Garbage collect the hasn't-been-used-in-years
GDT update IPI.

Tested by many; ok mikeb@, kettenis@

The LDT is only used by dead compat code now, so load the ldt
register with the null selector (disabling use of it), stop reloading
it on every context switch, and blow away the table itself, as well
as the pcb and pmap bits that were used to track it. Also, delete
two other unused pcb members: pcb_usersp and pcb_flags. (Deleting
pcb_usersp also keeps the pcb_savefpu member aligned properly.)
Finally, delete the defines for the unimplemented AMD64_{GET,SET}_LDT
sysarch() calls.

Tested by various with both AMD and Intel chips
ok mikeb@

Clean up segment handling: switch user-space to using code and data
segments in the GDT instead of the LDT and eliminate the GDT slots
that we don't actually use.

tested on both amd and intel by several
not really the right person, but ok: kettenis@

- remove USER_LDT, it was never in a state where it would copile, nor will
we support i386-compat mode on amd64.

agreed by beck@, dlg@, kettenis@
ok deraadt@, tom@

Remove the advertising clause in the UCB license which Berkeley
rescinded 22 July 1999.
Checked by ian@, deraadt@ and millert@, arm portion checked by drahn@

put int into a type

check struct reg for evil; from netbsd

an amd64 arch support.
hacked by art@ from netbsd sources and then later debugged
by me into the shape where it can host itself.
no bootloader yet as needs redoing from the
recent advanced i386 sources (anyone? ;)

Implement Multiple Message MSI support on amd64. This is experimental code
to assist qwx(4) development. We may remove this code again at some point
in the future.

Multiple Message MSI has some serious design flaws, especially when
combined with the APIC interrupt controller architecture. It was
superseded by MSI-X. Unfortunately qwx(4) does not implement MSI-X.

ok stsp@, deraadt@

Explicitly declare the gdt storage in struct cpu_info_full instead of
implicitly putting it in the padding to page-size. This eliminates a
couple Coverity issues from the Meltdown work.

testing daniel@
ok mlarkin@

How about I delete _all_ the BITFIELDTYPE comments?

lint is dead: BITFIELDTYPE comments aren't useful

ok miller@

LDT is gone and not coming back

Treat primary cpu like others and put pointer to its GDT in cpu_info.ci_gdt

requested by and ok mlarkin@

Normalize sentinel. Use _MACHINE_*_H_ and _<ARCH>_*_H_ properly and consitently.

Discussed and okay drahn@. Okay deraadt@.

__attribute__((packed)) -> __packed. The ioprbs.c chunk was commented out, and
uncommenting it is intentional.
ok deraadt@

Switch from TSS-per-process to TSS-per-CPU, placing the TSS right
next to the cpu's GDT, also making the double-fault stack per-CPU,
leaving it at the top of the page of the CPU's idle process. Inline
pmap_activate() and pmap_deactivate() into the asm cpu_switchto
routine, adding a check for the new pmap already being marked as
active on the CPU. Garbage collect the hasn't-been-used-in-years
GDT update IPI.

Tested by many; ok mikeb@, kettenis@

The LDT is only used by dead compat code now, so load the ldt
register with the null selector (disabling use of it), stop reloading
it on every context switch, and blow away the table itself, as well
as the pcb and pmap bits that were used to track it. Also, delete
two other unused pcb members: pcb_usersp and pcb_flags. (Deleting
pcb_usersp also keeps the pcb_savefpu member aligned properly.)
Finally, delete the defines for the unimplemented AMD64_{GET,SET}_LDT
sysarch() calls.

Tested by various with both AMD and Intel chips
ok mikeb@

Clean up segment handling: switch user-space to using code and data
segments in the GDT instead of the LDT and eliminate the GDT slots
that we don't actually use.

tested on both amd and intel by several
not really the right person, but ok: kettenis@

- remove USER_LDT, it was never in a state where it would copile, nor will
we support i386-compat mode on amd64.

agreed by beck@, dlg@, kettenis@
ok deraadt@, tom@

Remove the advertising clause in the UCB license which Berkeley
rescinded 22 July 1999.
Checked by ian@, deraadt@ and millert@, arm portion checked by drahn@

put int into a type

check struct reg for evil; from netbsd

an amd64 arch support.
hacked by art@ from netbsd sources and then later debugged
by me into the shape where it can host itself.
no bootloader yet as needs redoing from the
recent advanced i386 sources (anyone? ;)

Explicitly declare the gdt storage in struct cpu_info_full instead of
implicitly putting it in the padding to page-size. This eliminates a
couple Coverity issues from the Meltdown work.

testing daniel@
ok mlarkin@

How about I delete _all_ the BITFIELDTYPE comments?

lint is dead: BITFIELDTYPE comments aren't useful

ok miller@

LDT is gone and not coming back

Treat primary cpu like others and put pointer to its GDT in cpu_info.ci_gdt

requested by and ok mlarkin@

Normalize sentinel. Use _MACHINE_*_H_ and _<ARCH>_*_H_ properly and consitently.

Discussed and okay drahn@. Okay deraadt@.

__attribute__((packed)) -> __packed. The ioprbs.c chunk was commented out, and
uncommenting it is intentional.
ok deraadt@

Switch from TSS-per-process to TSS-per-CPU, placing the TSS right
next to the cpu's GDT, also making the double-fault stack per-CPU,
leaving it at the top of the page of the CPU's idle process. Inline
pmap_activate() and pmap_deactivate() into the asm cpu_switchto
routine, adding a check for the new pmap already being marked as
active on the CPU. Garbage collect the hasn't-been-used-in-years
GDT update IPI.

Tested by many; ok mikeb@, kettenis@

The LDT is only used by dead compat code now, so load the ldt
register with the null selector (disabling use of it), stop reloading
it on every context switch, and blow away the table itself, as well
as the pcb and pmap bits that were used to track it. Also, delete
two other unused pcb members: pcb_usersp and pcb_flags. (Deleting
pcb_usersp also keeps the pcb_savefpu member aligned properly.)
Finally, delete the defines for the unimplemented AMD64_{GET,SET}_LDT
sysarch() calls.

Tested by various with both AMD and Intel chips
ok mikeb@

Clean up segment handling: switch user-space to using code and data
segments in the GDT instead of the LDT and eliminate the GDT slots
that we don't actually use.

tested on both amd and intel by several
not really the right person, but ok: kettenis@

- remove USER_LDT, it was never in a state where it would copile, nor will
we support i386-compat mode on amd64.

agreed by beck@, dlg@, kettenis@
ok deraadt@, tom@

Remove the advertising clause in the UCB license which Berkeley
rescinded 22 July 1999.
Checked by ian@, deraadt@ and millert@, arm portion checked by drahn@

put int into a type

check struct reg for evil; from netbsd

an amd64 arch support.
hacked by art@ from netbsd sources and then later debugged
by me into the shape where it can host itself.
no bootloader yet as needs redoing from the
recent advanced i386 sources (anyone? ;)

How about I delete _all_ the BITFIELDTYPE comments?

lint is dead: BITFIELDTYPE comments aren't useful

ok miller@

LDT is gone and not coming back

Treat primary cpu like others and put pointer to its GDT in cpu_info.ci_gdt

requested by and ok mlarkin@

Normalize sentinel. Use _MACHINE_*_H_ and _<ARCH>_*_H_ properly and consitently.

Discussed and okay drahn@. Okay deraadt@.

__attribute__((packed)) -> __packed. The ioprbs.c chunk was commented out, and
uncommenting it is intentional.
ok deraadt@

Switch from TSS-per-process to TSS-per-CPU, placing the TSS right
next to the cpu's GDT, also making the double-fault stack per-CPU,
leaving it at the top of the page of the CPU's idle process. Inline
pmap_activate() and pmap_deactivate() into the asm cpu_switchto
routine, adding a check for the new pmap already being marked as
active on the CPU. Garbage collect the hasn't-been-used-in-years
GDT update IPI.

Tested by many; ok mikeb@, kettenis@

The LDT is only used by dead compat code now, so load the ldt
register with the null selector (disabling use of it), stop reloading
it on every context switch, and blow away the table itself, as well
as the pcb and pmap bits that were used to track it. Also, delete
two other unused pcb members: pcb_usersp and pcb_flags. (Deleting
pcb_usersp also keeps the pcb_savefpu member aligned properly.)
Finally, delete the defines for the unimplemented AMD64_{GET,SET}_LDT
sysarch() calls.

Tested by various with both AMD and Intel chips
ok mikeb@

Clean up segment handling: switch user-space to using code and data
segments in the GDT instead of the LDT and eliminate the GDT slots
that we don't actually use.

tested on both amd and intel by several
not really the right person, but ok: kettenis@

- remove USER_LDT, it was never in a state where it would copile, nor will
we support i386-compat mode on amd64.

agreed by beck@, dlg@, kettenis@
ok deraadt@, tom@

Remove the advertising clause in the UCB license which Berkeley
rescinded 22 July 1999.
Checked by ian@, deraadt@ and millert@, arm portion checked by drahn@

put int into a type

check struct reg for evil; from netbsd

an amd64 arch support.
hacked by art@ from netbsd sources and then later debugged
by me into the shape where it can host itself.
no bootloader yet as needs redoing from the
recent advanced i386 sources (anyone? ;)