Implement support for AVX-512. This required some fixes to the so-far
unused Skylake AVX-512 MDS handler and increases the ci_mds_tmp array to
64 bytes. With help from guenther@

ok deraadt@, guenther@

Enable Indirect Branch Tracking for amd64 userland, using XSAVES/XRSTORS
to save/restore the state and enabling it at exec-time (and for
signal handling) if the PS_NOBTCFI flag isn't set.

Note: this changes the format of the sc_fpstate data in the signal
context to possibly be in compressed format: starting now we just
guarantee that that state is in a format understood by the XRSTOR
instruction of the system that is being executed on.

At this time, passing sigreturn a corrupt sc_fpstate now results
in the process exiting with no attempt to fix it up or send a
T_PROTFLT trap. That may change.

prodding by deraadt@
issues with my original signal handling design identified by kettenis@

lots of base and ports preparation for this by deraadt@ and the
libressl and ports teams

ok deraadt@ kettenis@

The fp_ex_[st]w struct savefpu members were inherited from NetBSD where
they're used in the 32bit-compat support, which we dropped years ago.
Bye bye!

ok deraadt@

Fix size of reserved bytes section in xsave header.
ok guenther@ kettenis@

In vmm, handle xsetbv like xrstor: instead of trying to prevalidate
the values, just try it and handle the #GP if it faults.

Problem reported by Maxime Villard (max(at)m00nbsd.net)
ok mlarkin@

Move signal generation from fputrap() to where it's called in trap()

Switch from lazy FPU switching to semi-eager FPU switching: track whether
curproc's xstate ("extended state") is loaded in the CPU or not.
- context switch, sendsig(), vmm, and doing CPU crypto in the kernel all
check the flag and, if set, save the old thread's state to the PCB,
clear the flag, and then load the _blank_ state
- when returning to userspace, if the flag is clear then set it and restore
the thread's state

This simpler tracking also fixes the restoring of FPU state after nested
signal handlers.

With this, %cr0's TS flag is never set, the FPU #DNA trap can no
longer happen, and IPIs are no longer necessary for flushing or
syncing FPU state; on the other hand, restoring xstate while returning
to userspace means we have to handle xrstor faulting if we could
be loading an altered state. If that happens, reset the state,
fake a #GP fault (SIGBUS), and recheck for ASTs.

While here, regularize fxsave/fxrstor vs xsave/xrstor handling, by
using codepatching to switch to xsave/xrstor when present in the
CPU. In addition, code patch in use of xsaveopt in most places
when the CPU supports that. Use the 64bit-wide variants of the
instructions in all cases so that x87 instruction fault IPs are
reported correctly.

This change has three motivations:
1) with modern clang, SSE registers are used even in rcrt0.o, making
lazy FPU switching a smaller benefit vs trap costs
2) the Intel SDM warns that lazy FPU switching may increase power costs
3) post-Spectre rumors suggest that the %cr0 TS flag might not block
speculation, permitting leaking of information about FPU state
(AES keys?) across protection boundaries.

tested by many in snaps; prodding from deraadt@

Update comment to reflect xsave

branches: 1.12.2; 1.12.4;
vmm(4): proper save/restore of FPU context during entry/exit.

tested by reyk, dcoppa, and a few others.

ok kettenis@ on the fpu bits
ok deraadt@ on the vmm bits

branches: 1.11.10;
Save/restore AVX registers and other XSAVE-managed state information when
entering/leaving a signal handler like we already do the the FPU and SSE
state. This should make it possible to use AVX instructions in signal
handlers.

ok mlarkin@

Add support for saving/restoring FPU state using the XSAVE/XRSTOR. Limit
support to the X87, SSE and AVX state.

This gives us (almost) full AVX support. The AVX state isn't saved by
signal handlers yet, and ptrace(2) support is still missing.

ok guenther@

Normalize sentinel. Use _MACHINE_*_H_ and _<ARCH>_*_H_ properly and consitently.

Discussed and okay drahn@. Okay deraadt@.

When reading MXCSR from userland sigcontext or a ptrace request,
mask out invalid bits to prevent a protect fault.

Original diff by joshe@; further feedback and ok kettenis@

__attribute__((packed)) -> __packed. The ioprbs.c chunk was commented out, and
uncommenting it is intentional.
ok deraadt@

Back out previous, it appears to be broken.

When reading MXCSR from userland sigcontext, mask out invalid bits.

This prevents a protection fault if a userland signal handler
scribbles all over it's struct sigcontext

Help from and ok guenther@ kettenis@

fpu_kernel_{enter,exit}; Functions to allow the use of
the FPU in the kernel.

From Mike Belopuhov; Little bits by myself.

Comments/OK kettenis@

Switch fpu control word to the hardware default. This makes us use 64-bit
precision instead of 53-bit precision, giving us proper support for
"long double".

ok deraadt@

rename our NPXCW setting

branches: 1.1.2;
an amd64 arch support.
hacked by art@ from netbsd sources and then later debugged
by me into the shape where it can host itself.
no bootloader yet as needs redoing from the
recent advanced i386 sources (anyone? ;)

Enable Indirect Branch Tracking for amd64 userland, using XSAVES/XRSTORS
to save/restore the state and enabling it at exec-time (and for
signal handling) if the PS_NOBTCFI flag isn't set.

Note: this changes the format of the sc_fpstate data in the signal
context to possibly be in compressed format: starting now we just
guarantee that that state is in a format understood by the XRSTOR
instruction of the system that is being executed on.

At this time, passing sigreturn a corrupt sc_fpstate now results
in the process exiting with no attempt to fix it up or send a
T_PROTFLT trap. That may change.

prodding by deraadt@
issues with my original signal handling design identified by kettenis@

lots of base and ports preparation for this by deraadt@ and the
libressl and ports teams

ok deraadt@ kettenis@

The fp_ex_[st]w struct savefpu members were inherited from NetBSD where
they're used in the 32bit-compat support, which we dropped years ago.
Bye bye!

ok deraadt@

Fix size of reserved bytes section in xsave header.
ok guenther@ kettenis@

In vmm, handle xsetbv like xrstor: instead of trying to prevalidate
the values, just try it and handle the #GP if it faults.

Problem reported by Maxime Villard (max(at)m00nbsd.net)
ok mlarkin@

Move signal generation from fputrap() to where it's called in trap()

Switch from lazy FPU switching to semi-eager FPU switching: track whether
curproc's xstate ("extended state") is loaded in the CPU or not.
- context switch, sendsig(), vmm, and doing CPU crypto in the kernel all
check the flag and, if set, save the old thread's state to the PCB,
clear the flag, and then load the _blank_ state
- when returning to userspace, if the flag is clear then set it and restore
the thread's state

This simpler tracking also fixes the restoring of FPU state after nested
signal handlers.

With this, %cr0's TS flag is never set, the FPU #DNA trap can no
longer happen, and IPIs are no longer necessary for flushing or
syncing FPU state; on the other hand, restoring xstate while returning
to userspace means we have to handle xrstor faulting if we could
be loading an altered state. If that happens, reset the state,
fake a #GP fault (SIGBUS), and recheck for ASTs.

While here, regularize fxsave/fxrstor vs xsave/xrstor handling, by
using codepatching to switch to xsave/xrstor when present in the
CPU. In addition, code patch in use of xsaveopt in most places
when the CPU supports that. Use the 64bit-wide variants of the
instructions in all cases so that x87 instruction fault IPs are
reported correctly.

This change has three motivations:
1) with modern clang, SSE registers are used even in rcrt0.o, making
lazy FPU switching a smaller benefit vs trap costs
2) the Intel SDM warns that lazy FPU switching may increase power costs
3) post-Spectre rumors suggest that the %cr0 TS flag might not block
speculation, permitting leaking of information about FPU state
(AES keys?) across protection boundaries.

tested by many in snaps; prodding from deraadt@

Update comment to reflect xsave

branches: 1.12.2; 1.12.4;
vmm(4): proper save/restore of FPU context during entry/exit.

tested by reyk, dcoppa, and a few others.

ok kettenis@ on the fpu bits
ok deraadt@ on the vmm bits

branches: 1.11.10;
Save/restore AVX registers and other XSAVE-managed state information when
entering/leaving a signal handler like we already do the the FPU and SSE
state. This should make it possible to use AVX instructions in signal
handlers.

ok mlarkin@

Add support for saving/restoring FPU state using the XSAVE/XRSTOR. Limit
support to the X87, SSE and AVX state.

This gives us (almost) full AVX support. The AVX state isn't saved by
signal handlers yet, and ptrace(2) support is still missing.

ok guenther@

Normalize sentinel. Use _MACHINE_*_H_ and _<ARCH>_*_H_ properly and consitently.

Discussed and okay drahn@. Okay deraadt@.

When reading MXCSR from userland sigcontext or a ptrace request,
mask out invalid bits to prevent a protect fault.

Original diff by joshe@; further feedback and ok kettenis@

__attribute__((packed)) -> __packed. The ioprbs.c chunk was commented out, and
uncommenting it is intentional.
ok deraadt@

Back out previous, it appears to be broken.

When reading MXCSR from userland sigcontext, mask out invalid bits.

This prevents a protection fault if a userland signal handler
scribbles all over it's struct sigcontext

Help from and ok guenther@ kettenis@

fpu_kernel_{enter,exit}; Functions to allow the use of
the FPU in the kernel.

From Mike Belopuhov; Little bits by myself.

Comments/OK kettenis@

Switch fpu control word to the hardware default. This makes us use 64-bit
precision instead of 53-bit precision, giving us proper support for
"long double".

ok deraadt@

rename our NPXCW setting

branches: 1.1.2;
an amd64 arch support.
hacked by art@ from netbsd sources and then later debugged
by me into the shape where it can host itself.
no bootloader yet as needs redoing from the
recent advanced i386 sources (anyone? ;)

The fp_ex_[st]w struct savefpu members were inherited from NetBSD where
they're used in the 32bit-compat support, which we dropped years ago.
Bye bye!

ok deraadt@

Fix size of reserved bytes section in xsave header.
ok guenther@ kettenis@

In vmm, handle xsetbv like xrstor: instead of trying to prevalidate
the values, just try it and handle the #GP if it faults.

Problem reported by Maxime Villard (max(at)m00nbsd.net)
ok mlarkin@

Move signal generation from fputrap() to where it's called in trap()

Switch from lazy FPU switching to semi-eager FPU switching: track whether
curproc's xstate ("extended state") is loaded in the CPU or not.
- context switch, sendsig(), vmm, and doing CPU crypto in the kernel all
check the flag and, if set, save the old thread's state to the PCB,
clear the flag, and then load the _blank_ state
- when returning to userspace, if the flag is clear then set it and restore
the thread's state

This simpler tracking also fixes the restoring of FPU state after nested
signal handlers.

With this, %cr0's TS flag is never set, the FPU #DNA trap can no
longer happen, and IPIs are no longer necessary for flushing or
syncing FPU state; on the other hand, restoring xstate while returning
to userspace means we have to handle xrstor faulting if we could
be loading an altered state. If that happens, reset the state,
fake a #GP fault (SIGBUS), and recheck for ASTs.

While here, regularize fxsave/fxrstor vs xsave/xrstor handling, by
using codepatching to switch to xsave/xrstor when present in the
CPU. In addition, code patch in use of xsaveopt in most places
when the CPU supports that. Use the 64bit-wide variants of the
instructions in all cases so that x87 instruction fault IPs are
reported correctly.

This change has three motivations:
1) with modern clang, SSE registers are used even in rcrt0.o, making
lazy FPU switching a smaller benefit vs trap costs
2) the Intel SDM warns that lazy FPU switching may increase power costs
3) post-Spectre rumors suggest that the %cr0 TS flag might not block
speculation, permitting leaking of information about FPU state
(AES keys?) across protection boundaries.

tested by many in snaps; prodding from deraadt@

Update comment to reflect xsave

branches: 1.12.2; 1.12.4;
vmm(4): proper save/restore of FPU context during entry/exit.

tested by reyk, dcoppa, and a few others.

ok kettenis@ on the fpu bits
ok deraadt@ on the vmm bits

branches: 1.11.10;
Save/restore AVX registers and other XSAVE-managed state information when
entering/leaving a signal handler like we already do the the FPU and SSE
state. This should make it possible to use AVX instructions in signal
handlers.

ok mlarkin@

Add support for saving/restoring FPU state using the XSAVE/XRSTOR. Limit
support to the X87, SSE and AVX state.

This gives us (almost) full AVX support. The AVX state isn't saved by
signal handlers yet, and ptrace(2) support is still missing.

ok guenther@

Normalize sentinel. Use _MACHINE_*_H_ and _<ARCH>_*_H_ properly and consitently.

Discussed and okay drahn@. Okay deraadt@.

When reading MXCSR from userland sigcontext or a ptrace request,
mask out invalid bits to prevent a protect fault.

Original diff by joshe@; further feedback and ok kettenis@

__attribute__((packed)) -> __packed. The ioprbs.c chunk was commented out, and
uncommenting it is intentional.
ok deraadt@

Back out previous, it appears to be broken.

When reading MXCSR from userland sigcontext, mask out invalid bits.

This prevents a protection fault if a userland signal handler
scribbles all over it's struct sigcontext

Help from and ok guenther@ kettenis@

fpu_kernel_{enter,exit}; Functions to allow the use of
the FPU in the kernel.

From Mike Belopuhov; Little bits by myself.

Comments/OK kettenis@

Switch fpu control word to the hardware default. This makes us use 64-bit
precision instead of 53-bit precision, giving us proper support for
"long double".

ok deraadt@

rename our NPXCW setting

branches: 1.1.2;
an amd64 arch support.
hacked by art@ from netbsd sources and then later debugged
by me into the shape where it can host itself.
no bootloader yet as needs redoing from the
recent advanced i386 sources (anyone? ;)

Fix size of reserved bytes section in xsave header.
ok guenther@ kettenis@

In vmm, handle xsetbv like xrstor: instead of trying to prevalidate
the values, just try it and handle the #GP if it faults.

Problem reported by Maxime Villard (max(at)m00nbsd.net)
ok mlarkin@

Move signal generation from fputrap() to where it's called in trap()

Switch from lazy FPU switching to semi-eager FPU switching: track whether
curproc's xstate ("extended state") is loaded in the CPU or not.
- context switch, sendsig(), vmm, and doing CPU crypto in the kernel all
check the flag and, if set, save the old thread's state to the PCB,
clear the flag, and then load the _blank_ state
- when returning to userspace, if the flag is clear then set it and restore
the thread's state

This simpler tracking also fixes the restoring of FPU state after nested
signal handlers.

With this, %cr0's TS flag is never set, the FPU #DNA trap can no
longer happen, and IPIs are no longer necessary for flushing or
syncing FPU state; on the other hand, restoring xstate while returning
to userspace means we have to handle xrstor faulting if we could
be loading an altered state. If that happens, reset the state,
fake a #GP fault (SIGBUS), and recheck for ASTs.

While here, regularize fxsave/fxrstor vs xsave/xrstor handling, by
using codepatching to switch to xsave/xrstor when present in the
CPU. In addition, code patch in use of xsaveopt in most places
when the CPU supports that. Use the 64bit-wide variants of the
instructions in all cases so that x87 instruction fault IPs are
reported correctly.

This change has three motivations:
1) with modern clang, SSE registers are used even in rcrt0.o, making
lazy FPU switching a smaller benefit vs trap costs
2) the Intel SDM warns that lazy FPU switching may increase power costs
3) post-Spectre rumors suggest that the %cr0 TS flag might not block
speculation, permitting leaking of information about FPU state
(AES keys?) across protection boundaries.

tested by many in snaps; prodding from deraadt@

Update comment to reflect xsave

branches: 1.12.2; 1.12.4;
vmm(4): proper save/restore of FPU context during entry/exit.

tested by reyk, dcoppa, and a few others.

ok kettenis@ on the fpu bits
ok deraadt@ on the vmm bits

branches: 1.11.10;
Save/restore AVX registers and other XSAVE-managed state information when
entering/leaving a signal handler like we already do the the FPU and SSE
state. This should make it possible to use AVX instructions in signal
handlers.

ok mlarkin@

Add support for saving/restoring FPU state using the XSAVE/XRSTOR. Limit
support to the X87, SSE and AVX state.

This gives us (almost) full AVX support. The AVX state isn't saved by
signal handlers yet, and ptrace(2) support is still missing.

ok guenther@

Normalize sentinel. Use _MACHINE_*_H_ and _<ARCH>_*_H_ properly and consitently.

Discussed and okay drahn@. Okay deraadt@.

When reading MXCSR from userland sigcontext or a ptrace request,
mask out invalid bits to prevent a protect fault.

Original diff by joshe@; further feedback and ok kettenis@

__attribute__((packed)) -> __packed. The ioprbs.c chunk was commented out, and
uncommenting it is intentional.
ok deraadt@

Back out previous, it appears to be broken.

When reading MXCSR from userland sigcontext, mask out invalid bits.

This prevents a protection fault if a userland signal handler
scribbles all over it's struct sigcontext

Help from and ok guenther@ kettenis@

fpu_kernel_{enter,exit}; Functions to allow the use of
the FPU in the kernel.

From Mike Belopuhov; Little bits by myself.

Comments/OK kettenis@

Switch fpu control word to the hardware default. This makes us use 64-bit
precision instead of 53-bit precision, giving us proper support for
"long double".

ok deraadt@

rename our NPXCW setting

branches: 1.1.2;
an amd64 arch support.
hacked by art@ from netbsd sources and then later debugged
by me into the shape where it can host itself.
no bootloader yet as needs redoing from the
recent advanced i386 sources (anyone? ;)

In vmm, handle xsetbv like xrstor: instead of trying to prevalidate
the values, just try it and handle the #GP if it faults.

Problem reported by Maxime Villard (max(at)m00nbsd.net)
ok mlarkin@

Move signal generation from fputrap() to where it's called in trap()

Switch from lazy FPU switching to semi-eager FPU switching: track whether
curproc's xstate ("extended state") is loaded in the CPU or not.
- context switch, sendsig(), vmm, and doing CPU crypto in the kernel all
check the flag and, if set, save the old thread's state to the PCB,
clear the flag, and then load the _blank_ state
- when returning to userspace, if the flag is clear then set it and restore
the thread's state

This simpler tracking also fixes the restoring of FPU state after nested
signal handlers.

With this, %cr0's TS flag is never set, the FPU #DNA trap can no
longer happen, and IPIs are no longer necessary for flushing or
syncing FPU state; on the other hand, restoring xstate while returning
to userspace means we have to handle xrstor faulting if we could
be loading an altered state. If that happens, reset the state,
fake a #GP fault (SIGBUS), and recheck for ASTs.

While here, regularize fxsave/fxrstor vs xsave/xrstor handling, by
using codepatching to switch to xsave/xrstor when present in the
CPU. In addition, code patch in use of xsaveopt in most places
when the CPU supports that. Use the 64bit-wide variants of the
instructions in all cases so that x87 instruction fault IPs are
reported correctly.

This change has three motivations:
1) with modern clang, SSE registers are used even in rcrt0.o, making
lazy FPU switching a smaller benefit vs trap costs
2) the Intel SDM warns that lazy FPU switching may increase power costs
3) post-Spectre rumors suggest that the %cr0 TS flag might not block
speculation, permitting leaking of information about FPU state
(AES keys?) across protection boundaries.

tested by many in snaps; prodding from deraadt@

Update comment to reflect xsave

branches: 1.12.2; 1.12.4;
vmm(4): proper save/restore of FPU context during entry/exit.

tested by reyk, dcoppa, and a few others.

ok kettenis@ on the fpu bits
ok deraadt@ on the vmm bits

branches: 1.11.10;
Save/restore AVX registers and other XSAVE-managed state information when
entering/leaving a signal handler like we already do the the FPU and SSE
state. This should make it possible to use AVX instructions in signal
handlers.

ok mlarkin@

Add support for saving/restoring FPU state using the XSAVE/XRSTOR. Limit
support to the X87, SSE and AVX state.

This gives us (almost) full AVX support. The AVX state isn't saved by
signal handlers yet, and ptrace(2) support is still missing.

ok guenther@

Normalize sentinel. Use _MACHINE_*_H_ and _<ARCH>_*_H_ properly and consitently.

Discussed and okay drahn@. Okay deraadt@.

When reading MXCSR from userland sigcontext or a ptrace request,
mask out invalid bits to prevent a protect fault.

Original diff by joshe@; further feedback and ok kettenis@

__attribute__((packed)) -> __packed. The ioprbs.c chunk was commented out, and
uncommenting it is intentional.
ok deraadt@

Back out previous, it appears to be broken.

When reading MXCSR from userland sigcontext, mask out invalid bits.

This prevents a protection fault if a userland signal handler
scribbles all over it's struct sigcontext

Help from and ok guenther@ kettenis@

fpu_kernel_{enter,exit}; Functions to allow the use of
the FPU in the kernel.

From Mike Belopuhov; Little bits by myself.

Comments/OK kettenis@

Switch fpu control word to the hardware default. This makes us use 64-bit
precision instead of 53-bit precision, giving us proper support for
"long double".

ok deraadt@

rename our NPXCW setting

branches: 1.1.2;
an amd64 arch support.
hacked by art@ from netbsd sources and then later debugged
by me into the shape where it can host itself.
no bootloader yet as needs redoing from the
recent advanced i386 sources (anyone? ;)

Move signal generation from fputrap() to where it's called in trap()

Switch from lazy FPU switching to semi-eager FPU switching: track whether
curproc's xstate ("extended state") is loaded in the CPU or not.
- context switch, sendsig(), vmm, and doing CPU crypto in the kernel all
check the flag and, if set, save the old thread's state to the PCB,
clear the flag, and then load the _blank_ state
- when returning to userspace, if the flag is clear then set it and restore
the thread's state

This simpler tracking also fixes the restoring of FPU state after nested
signal handlers.

With this, %cr0's TS flag is never set, the FPU #DNA trap can no
longer happen, and IPIs are no longer necessary for flushing or
syncing FPU state; on the other hand, restoring xstate while returning
to userspace means we have to handle xrstor faulting if we could
be loading an altered state. If that happens, reset the state,
fake a #GP fault (SIGBUS), and recheck for ASTs.

While here, regularize fxsave/fxrstor vs xsave/xrstor handling, by
using codepatching to switch to xsave/xrstor when present in the
CPU. In addition, code patch in use of xsaveopt in most places
when the CPU supports that. Use the 64bit-wide variants of the
instructions in all cases so that x87 instruction fault IPs are
reported correctly.

This change has three motivations:
1) with modern clang, SSE registers are used even in rcrt0.o, making
lazy FPU switching a smaller benefit vs trap costs
2) the Intel SDM warns that lazy FPU switching may increase power costs
3) post-Spectre rumors suggest that the %cr0 TS flag might not block
speculation, permitting leaking of information about FPU state
(AES keys?) across protection boundaries.

tested by many in snaps; prodding from deraadt@

Update comment to reflect xsave

branches: 1.12.2; 1.12.4;
vmm(4): proper save/restore of FPU context during entry/exit.

tested by reyk, dcoppa, and a few others.

ok kettenis@ on the fpu bits
ok deraadt@ on the vmm bits

branches: 1.11.10;
Save/restore AVX registers and other XSAVE-managed state information when
entering/leaving a signal handler like we already do the the FPU and SSE
state. This should make it possible to use AVX instructions in signal
handlers.

ok mlarkin@

Add support for saving/restoring FPU state using the XSAVE/XRSTOR. Limit
support to the X87, SSE and AVX state.

This gives us (almost) full AVX support. The AVX state isn't saved by
signal handlers yet, and ptrace(2) support is still missing.

ok guenther@

Normalize sentinel. Use _MACHINE_*_H_ and _<ARCH>_*_H_ properly and consitently.

Discussed and okay drahn@. Okay deraadt@.

When reading MXCSR from userland sigcontext or a ptrace request,
mask out invalid bits to prevent a protect fault.

Original diff by joshe@; further feedback and ok kettenis@

__attribute__((packed)) -> __packed. The ioprbs.c chunk was commented out, and
uncommenting it is intentional.
ok deraadt@

Back out previous, it appears to be broken.

When reading MXCSR from userland sigcontext, mask out invalid bits.

This prevents a protection fault if a userland signal handler
scribbles all over it's struct sigcontext

Help from and ok guenther@ kettenis@

fpu_kernel_{enter,exit}; Functions to allow the use of
the FPU in the kernel.

From Mike Belopuhov; Little bits by myself.

Comments/OK kettenis@

Switch fpu control word to the hardware default. This makes us use 64-bit
precision instead of 53-bit precision, giving us proper support for
"long double".

ok deraadt@

rename our NPXCW setting

branches: 1.1.2;
an amd64 arch support.
hacked by art@ from netbsd sources and then later debugged
by me into the shape where it can host itself.
no bootloader yet as needs redoing from the
recent advanced i386 sources (anyone? ;)

vmm(4): proper save/restore of FPU context during entry/exit.

tested by reyk, dcoppa, and a few others.

ok kettenis@ on the fpu bits
ok deraadt@ on the vmm bits

branches: 1.11.10;
Save/restore AVX registers and other XSAVE-managed state information when
entering/leaving a signal handler like we already do the the FPU and SSE
state. This should make it possible to use AVX instructions in signal
handlers.

ok mlarkin@

Add support for saving/restoring FPU state using the XSAVE/XRSTOR. Limit
support to the X87, SSE and AVX state.

This gives us (almost) full AVX support. The AVX state isn't saved by
signal handlers yet, and ptrace(2) support is still missing.

ok guenther@

Normalize sentinel. Use _MACHINE_*_H_ and _<ARCH>_*_H_ properly and consitently.

Discussed and okay drahn@. Okay deraadt@.

When reading MXCSR from userland sigcontext or a ptrace request,
mask out invalid bits to prevent a protect fault.

Original diff by joshe@; further feedback and ok kettenis@

__attribute__((packed)) -> __packed. The ioprbs.c chunk was commented out, and
uncommenting it is intentional.
ok deraadt@

Back out previous, it appears to be broken.

When reading MXCSR from userland sigcontext, mask out invalid bits.

This prevents a protection fault if a userland signal handler
scribbles all over it's struct sigcontext

Help from and ok guenther@ kettenis@

fpu_kernel_{enter,exit}; Functions to allow the use of
the FPU in the kernel.

From Mike Belopuhov; Little bits by myself.

Comments/OK kettenis@

Switch fpu control word to the hardware default. This makes us use 64-bit
precision instead of 53-bit precision, giving us proper support for
"long double".

ok deraadt@

rename our NPXCW setting

branches: 1.1.2;
an amd64 arch support.
hacked by art@ from netbsd sources and then later debugged
by me into the shape where it can host itself.
no bootloader yet as needs redoing from the
recent advanced i386 sources (anyone? ;)