| #
1.4 |
|
27-Jan-2022 |
visa |
cad(4): Mention PolarFire SoC.
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|
Revision tags: OPENBSD_7_0_BASE
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|
| #
1.3 |
|
08-Sep-2021 |
jmc |
attempt to standardise the way we specify speeds in our name description (Nd)
lines;
sthen and deraadt argued for unit suffixes for speeds 1Gb+
deraadt also requested Gigabit be standardised to 1Gb
ok sthen deraadt ian benno
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| #
1.2 |
|
13-Jun-2021 |
jsg |
add SiFive FU740-C000 to SoC list
|
| #
1.1 |
|
28-May-2021 |
visa |
Add cad(4), a driver for Cadence GEM.
This initial revision targets the Zynq-7000, where the GEM implements
single transmit and receive queues with 32-bit DMA addresses. The driver
uses receive checksum offload, but transmit checksum offload is disabled
because of a hardware quirk. Also, the hardware's receive path is prone
to getting stuck if input cannot be handled quickly enough. The driver
attempts to recover by restarting the receiver when no input has been
seen for a while.
OK kettenis@
|
| #
1.3 |
|
08-Sep-2021 |
jmc |
attempt to standardise the way we specify speeds in our name description (Nd)
lines;
sthen and deraadt argued for unit suffixes for speeds 1Gb+
deraadt also requested Gigabit be standardised to 1Gb
ok sthen deraadt ian benno
|
| #
1.2 |
|
13-Jun-2021 |
jsg |
add SiFive FU740-C000 to SoC list
|
| #
1.1 |
|
28-May-2021 |
visa |
Add cad(4), a driver for Cadence GEM.
This initial revision targets the Zynq-7000, where the GEM implements
single transmit and receive queues with 32-bit DMA addresses. The driver
uses receive checksum offload, but transmit checksum offload is disabled
because of a hardware quirk. Also, the hardware's receive path is prone
to getting stuck if input cannot be handled quickly enough. The driver
attempts to recover by restarting the receiver when no input has been
seen for a while.
OK kettenis@
|
| #
1.2 |
|
13-Jun-2021 |
jsg |
add SiFive FU740-C000 to SoC list
|
| #
1.1 |
|
28-May-2021 |
visa |
Add cad(4), a driver for Cadence GEM.
This initial revision targets the Zynq-7000, where the GEM implements
single transmit and receive queues with 32-bit DMA addresses. The driver
uses receive checksum offload, but transmit checksum offload is disabled
because of a hardware quirk. Also, the hardware's receive path is prone
to getting stuck if input cannot be handled quickly enough. The driver
attempts to recover by restarting the receiver when no input has been
seen for a while.
OK kettenis@
|
| #
1.1 |
|
28-May-2021 |
visa |
Add cad(4), a driver for Cadence GEM.
This initial revision targets the Zynq-7000, where the GEM implements
single transmit and receive queues with 32-bit DMA addresses. The driver
uses receive checksum offload, but transmit checksum offload is disabled
because of a hardware quirk. Also, the hardware's receive path is prone
to getting stuck if input cannot be handled quickly enough. The driver
attempts to recover by restarting the receiver when no input has been
seen for a while.
OK kettenis@
|