KNF. No functional change.

Even if an overflow interrupt is occured for a counter outside tprof management,
the bit of onverflow status register must be cleared to prevent an interrupt storm.

branches: 1.18.2;
Improve tprof(4)

- Multiple events can now be handled simultaneously.
- Counters should be configured with TPROF_IOC_CONFIGURE_EVENT in advance,
instead of being configured at TPROF_IOC_START.
- The configured counters can be started and stopped repeatedly by
PROF_IOC_START/TPROF_IOC_STOP.
- The value of the performance counter can be obtained at any timing as a 64bit
value with TPROF_IOC_GETCOUNTS.
- Backend common parts are handled in tprof.c as much as possible, and functions
on the tprof_backend side have been reimplemented to be more primitive.
- The reset value of counter overflows for profiling can now be adjusted.
It is calculated by default from the CPU clock (speed of cycle counter) and
TPROF_HZ, but for some events the value may be too large to be sufficient for
profiling. The event counter can be specified as a ratio to the default or as
an absolute value when configuring the event counter.
- Due to overall changes, API and ABI have been changed. TPROF_VERSION and
TPROF_BACKEND_VERSION were updated.

PMCR.E should not be disabled from tprof.

PMCR.E controls not only performance event counters but also the cycle
counter operation, and the cycle counter may be used for cpu_counter.
Similarly, the 31st bit in PMINTENCLR and PMCNTENCLR controls the cycle
counter, not performance event counters, and should not be modified.

revert my previous commit.

since armv8_pmu_init is only called when it is reliably worked by ACPI or fdt,
there is no need for dynamic checks.

pointed out by jmcneill@, thanks

If the hardware does not support PMU, return an error instead of KASSERT.

tprof: armv8: Only attach to known PMU types.

fix the typo that martin spotted.

Add a comment and simplify the code ever so slightly.

Use the first (not second) event counter as there might only be one
available.

declare xc

Improve error handling.

Hypervisors can return a PMCR.N of 0.

Trailing whitespace

Make sure setup happens on all CPUs.

Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.

Enable the cycle counter when a CPU hatches and store an estimate of the
frequency in ci_data.cpu_cc_freq.

branches: 1.4.2; 1.4.8;
use PRI?64 instead of ll?

Spaces -> tabs

RW fields in performance monitor registers are reset to architecturally
UNKNOWN values. Initialize the PMU to a known state - all interrupts and
counters disabled, performance monitor disabled, and user access disabled.

Add tprof backend for ARMv8 performance monitors.

Even if an overflow interrupt is occured for a counter outside tprof management,
the bit of onverflow status register must be cleared to prevent an interrupt storm.

Improve tprof(4)

- Multiple events can now be handled simultaneously.
- Counters should be configured with TPROF_IOC_CONFIGURE_EVENT in advance,
instead of being configured at TPROF_IOC_START.
- The configured counters can be started and stopped repeatedly by
PROF_IOC_START/TPROF_IOC_STOP.
- The value of the performance counter can be obtained at any timing as a 64bit
value with TPROF_IOC_GETCOUNTS.
- Backend common parts are handled in tprof.c as much as possible, and functions
on the tprof_backend side have been reimplemented to be more primitive.
- The reset value of counter overflows for profiling can now be adjusted.
It is calculated by default from the CPU clock (speed of cycle counter) and
TPROF_HZ, but for some events the value may be too large to be sufficient for
profiling. The event counter can be specified as a ratio to the default or as
an absolute value when configuring the event counter.
- Due to overall changes, API and ABI have been changed. TPROF_VERSION and
TPROF_BACKEND_VERSION were updated.

PMCR.E should not be disabled from tprof.

PMCR.E controls not only performance event counters but also the cycle
counter operation, and the cycle counter may be used for cpu_counter.
Similarly, the 31st bit in PMINTENCLR and PMCNTENCLR controls the cycle
counter, not performance event counters, and should not be modified.

revert my previous commit.

since armv8_pmu_init is only called when it is reliably worked by ACPI or fdt,
there is no need for dynamic checks.

pointed out by jmcneill@, thanks

If the hardware does not support PMU, return an error instead of KASSERT.

tprof: armv8: Only attach to known PMU types.

fix the typo that martin spotted.

Add a comment and simplify the code ever so slightly.

Use the first (not second) event counter as there might only be one
available.

declare xc

Improve error handling.

Hypervisors can return a PMCR.N of 0.

Trailing whitespace

Make sure setup happens on all CPUs.

Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.

Enable the cycle counter when a CPU hatches and store an estimate of the
frequency in ci_data.cpu_cc_freq.

branches: 1.4.2; 1.4.8;
use PRI?64 instead of ll?

Spaces -> tabs

RW fields in performance monitor registers are reset to architecturally
UNKNOWN values. Initialize the PMU to a known state - all interrupts and
counters disabled, performance monitor disabled, and user access disabled.

Add tprof backend for ARMv8 performance monitors.

Improve tprof(4)

- Multiple events can now be handled simultaneously.
- Counters should be configured with TPROF_IOC_CONFIGURE_EVENT in advance,
instead of being configured at TPROF_IOC_START.
- The configured counters can be started and stopped repeatedly by
PROF_IOC_START/TPROF_IOC_STOP.
- The value of the performance counter can be obtained at any timing as a 64bit
value with TPROF_IOC_GETCOUNTS.
- Backend common parts are handled in tprof.c as much as possible, and functions
on the tprof_backend side have been reimplemented to be more primitive.
- The reset value of counter overflows for profiling can now be adjusted.
It is calculated by default from the CPU clock (speed of cycle counter) and
TPROF_HZ, but for some events the value may be too large to be sufficient for
profiling. The event counter can be specified as a ratio to the default or as
an absolute value when configuring the event counter.
- Due to overall changes, API and ABI have been changed. TPROF_VERSION and
TPROF_BACKEND_VERSION were updated.

PMCR.E should not be disabled from tprof.

PMCR.E controls not only performance event counters but also the cycle
counter operation, and the cycle counter may be used for cpu_counter.
Similarly, the 31st bit in PMINTENCLR and PMCNTENCLR controls the cycle
counter, not performance event counters, and should not be modified.

revert my previous commit.

since armv8_pmu_init is only called when it is reliably worked by ACPI or fdt,
there is no need for dynamic checks.

pointed out by jmcneill@, thanks

If the hardware does not support PMU, return an error instead of KASSERT.

tprof: armv8: Only attach to known PMU types.

fix the typo that martin spotted.

Add a comment and simplify the code ever so slightly.

Use the first (not second) event counter as there might only be one
available.

declare xc

Improve error handling.

Hypervisors can return a PMCR.N of 0.

Trailing whitespace

Make sure setup happens on all CPUs.

Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.

Enable the cycle counter when a CPU hatches and store an estimate of the
frequency in ci_data.cpu_cc_freq.

branches: 1.4.2; 1.4.8;
use PRI?64 instead of ll?

Spaces -> tabs

RW fields in performance monitor registers are reset to architecturally
UNKNOWN values. Initialize the PMU to a known state - all interrupts and
counters disabled, performance monitor disabled, and user access disabled.

Add tprof backend for ARMv8 performance monitors.

revert my previous commit.

since armv8_pmu_init is only called when it is reliably worked by ACPI or fdt,
there is no need for dynamic checks.

pointed out by jmcneill@, thanks

If the hardware does not support PMU, return an error instead of KASSERT.

tprof: armv8: Only attach to known PMU types.

fix the typo that martin spotted.

Add a comment and simplify the code ever so slightly.

Use the first (not second) event counter as there might only be one
available.

declare xc

Improve error handling.

Hypervisors can return a PMCR.N of 0.

Trailing whitespace

Make sure setup happens on all CPUs.

Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.

Enable the cycle counter when a CPU hatches and store an estimate of the
frequency in ci_data.cpu_cc_freq.

branches: 1.4.2; 1.4.8;
use PRI?64 instead of ll?

Spaces -> tabs

RW fields in performance monitor registers are reset to architecturally
UNKNOWN values. Initialize the PMU to a known state - all interrupts and
counters disabled, performance monitor disabled, and user access disabled.

Add tprof backend for ARMv8 performance monitors.

tprof: armv8: Only attach to known PMU types.

fix the typo that martin spotted.

Add a comment and simplify the code ever so slightly.

Use the first (not second) event counter as there might only be one
available.

declare xc

Improve error handling.

Hypervisors can return a PMCR.N of 0.

Trailing whitespace

Make sure setup happens on all CPUs.

Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.

Enable the cycle counter when a CPU hatches and store an estimate of the
frequency in ci_data.cpu_cc_freq.

branches: 1.4.2; 1.4.8;
use PRI?64 instead of ll?

Spaces -> tabs

RW fields in performance monitor registers are reset to architecturally
UNKNOWN values. Initialize the PMU to a known state - all interrupts and
counters disabled, performance monitor disabled, and user access disabled.

Add tprof backend for ARMv8 performance monitors.

fix the typo that martin spotted.

Add a comment and simplify the code ever so slightly.

Use the first (not second) event counter as there might only be one
available.

declare xc

Improve error handling.

Hypervisors can return a PMCR.N of 0.

Trailing whitespace

Make sure setup happens on all CPUs.

Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.

Enable the cycle counter when a CPU hatches and store an estimate of the
frequency in ci_data.cpu_cc_freq.

branches: 1.4.2; 1.4.8;
use PRI?64 instead of ll?

Spaces -> tabs

RW fields in performance monitor registers are reset to architecturally
UNKNOWN values. Initialize the PMU to a known state - all interrupts and
counters disabled, performance monitor disabled, and user access disabled.

Add tprof backend for ARMv8 performance monitors.

declare xc

Improve error handling.

Hypervisors can return a PMCR.N of 0.

Trailing whitespace

Make sure setup happens on all CPUs.

Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.

Enable the cycle counter when a CPU hatches and store an estimate of the
frequency in ci_data.cpu_cc_freq.

branches: 1.4.2; 1.4.8;
use PRI?64 instead of ll?

Spaces -> tabs

RW fields in performance monitor registers are reset to architecturally
UNKNOWN values. Initialize the PMU to a known state - all interrupts and
counters disabled, performance monitor disabled, and user access disabled.

Add tprof backend for ARMv8 performance monitors.

Improve error handling.

Hypervisors can return a PMCR.N of 0.

Trailing whitespace

Make sure setup happens on all CPUs.

Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.

Enable the cycle counter when a CPU hatches and store an estimate of the
frequency in ci_data.cpu_cc_freq.

branches: 1.4.2; 1.4.8;
use PRI?64 instead of ll?

Spaces -> tabs

RW fields in performance monitor registers are reset to architecturally
UNKNOWN values. Initialize the PMU to a known state - all interrupts and
counters disabled, performance monitor disabled, and user access disabled.

Add tprof backend for ARMv8 performance monitors.

Trailing whitespace

Make sure setup happens on all CPUs.

Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.

Enable the cycle counter when a CPU hatches and store an estimate of the
frequency in ci_data.cpu_cc_freq.

branches: 1.4.2; 1.4.8;
use PRI?64 instead of ll?

Spaces -> tabs

RW fields in performance monitor registers are reset to architecturally
UNKNOWN values. Initialize the PMU to a known state - all interrupts and
counters disabled, performance monitor disabled, and user access disabled.

Add tprof backend for ARMv8 performance monitors.

Make sure setup happens on all CPUs.

Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.

Enable the cycle counter when a CPU hatches and store an estimate of the
frequency in ci_data.cpu_cc_freq.

branches: 1.4.2; 1.4.8;
use PRI?64 instead of ll?

Spaces -> tabs

RW fields in performance monitor registers are reset to architecturally
UNKNOWN values. Initialize the PMU to a known state - all interrupts and
counters disabled, performance monitor disabled, and user access disabled.

Add tprof backend for ARMv8 performance monitors.

Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.

Enable the cycle counter when a CPU hatches and store an estimate of the
frequency in ci_data.cpu_cc_freq.

branches: 1.4.2; 1.4.8;
use PRI?64 instead of ll?

Spaces -> tabs

RW fields in performance monitor registers are reset to architecturally
UNKNOWN values. Initialize the PMU to a known state - all interrupts and
counters disabled, performance monitor disabled, and user access disabled.

Add tprof backend for ARMv8 performance monitors.

Enable the cycle counter when a CPU hatches and store an estimate of the
frequency in ci_data.cpu_cc_freq.

branches: 1.4.2; 1.4.8;
use PRI?64 instead of ll?

Spaces -> tabs

RW fields in performance monitor registers are reset to architecturally
UNKNOWN values. Initialize the PMU to a known state - all interrupts and
counters disabled, performance monitor disabled, and user access disabled.

Add tprof backend for ARMv8 performance monitors.