| #
1.6 |
|
02-May-2024 |
skrll |
risc-v: fix the error code when uvm_fault fails with cpu_set_onfault
Return the error from uvm_fault instead of EFAULT unconditionally when
faulting with cpu_set_onfault to fix several atf tests.
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|
Revision tags: thorpej-ifq-base thorpej-altq-separation-base
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| #
1.5 |
|
07-May-2023 |
skrll |
RISC-V support that works on QEMU with a single hart.
Thanks for Simon Burge for plic(4).
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| #
1.4 |
|
01-Mar-2023 |
riastradh |
riscv: Optimization: Omit needless membar when triggering softint.
When we are triggering a softint, it can't already hold any mutexes.
So any path to mutex_exit(mtx) must go via mutex_enter(mtx), which is
always done with atomic r/m/w, and we need not issue any explicit
barrier between ci->ci_curlwp = softlwp and a potential load of
mtx->mtx_owner in mutex_exit.
PR kern/57240
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| #
1.3 |
|
23-Feb-2023 |
riastradh |
riscv: Add missing barriers in cpu_switchto.
Details in comments.
PR kern/57240
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|
Revision tags: netbsd-10-base
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| #
1.2 |
|
04-Dec-2022 |
skrll |
branches: 1.2.2;
Restore t5 and t6 from the correct locations in exception_kernexit.
From Simon.
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| #
1.1 |
|
14-Oct-2022 |
skrll |
Split out a bunch of functions from locore.S into cpu_switch.S
NFC
|
| #
1.5 |
|
07-May-2023 |
skrll |
RISC-V support that works on QEMU with a single hart.
Thanks for Simon Burge for plic(4).
|
| #
1.4 |
|
01-Mar-2023 |
riastradh |
riscv: Optimization: Omit needless membar when triggering softint.
When we are triggering a softint, it can't already hold any mutexes.
So any path to mutex_exit(mtx) must go via mutex_enter(mtx), which is
always done with atomic r/m/w, and we need not issue any explicit
barrier between ci->ci_curlwp = softlwp and a potential load of
mtx->mtx_owner in mutex_exit.
PR kern/57240
|
| #
1.3 |
|
23-Feb-2023 |
riastradh |
riscv: Add missing barriers in cpu_switchto.
Details in comments.
PR kern/57240
|
|
Revision tags: netbsd-10-base
|
|
| #
1.2 |
|
04-Dec-2022 |
skrll |
Restore t5 and t6 from the correct locations in exception_kernexit.
From Simon.
|
| #
1.1 |
|
14-Oct-2022 |
skrll |
Split out a bunch of functions from locore.S into cpu_switch.S
NFC
|
| #
1.4 |
|
01-Mar-2023 |
riastradh |
riscv: Optimization: Omit needless membar when triggering softint.
When we are triggering a softint, it can't already hold any mutexes.
So any path to mutex_exit(mtx) must go via mutex_enter(mtx), which is
always done with atomic r/m/w, and we need not issue any explicit
barrier between ci->ci_curlwp = softlwp and a potential load of
mtx->mtx_owner in mutex_exit.
PR kern/57240
|
| #
1.3 |
|
23-Feb-2023 |
riastradh |
riscv: Add missing barriers in cpu_switchto.
Details in comments.
PR kern/57240
|
|
Revision tags: netbsd-10-base
|
|
| #
1.2 |
|
04-Dec-2022 |
skrll |
Restore t5 and t6 from the correct locations in exception_kernexit.
From Simon.
|
| #
1.1 |
|
14-Oct-2022 |
skrll |
Split out a bunch of functions from locore.S into cpu_switch.S
NFC
|
| #
1.3 |
|
23-Feb-2023 |
riastradh |
riscv: Add missing barriers in cpu_switchto.
Details in comments.
PR kern/57240
|
|
Revision tags: netbsd-10-base
|
|
| #
1.2 |
|
04-Dec-2022 |
skrll |
Restore t5 and t6 from the correct locations in exception_kernexit.
From Simon.
|
| #
1.1 |
|
14-Oct-2022 |
skrll |
Split out a bunch of functions from locore.S into cpu_switch.S
NFC
|
| #
1.2 |
|
04-Dec-2022 |
skrll |
Restore t5 and t6 from the correct locations in exception_kernexit.
From Simon.
|
| #
1.1 |
|
14-Oct-2022 |
skrll |
Split out a bunch of functions from locore.S into cpu_switch.S
NFC
|
| #
1.1 |
|
14-Oct-2022 |
skrll |
Split out a bunch of functions from locore.S into cpu_switch.S
NFC
|