don't do anything in vec_restore_from_mcontext() if no altivec.

fixes a crash seen on netbsd-10 in PR#58283.

XXX: pullup-10.

- In vec_restore_from_mcontext() and vec_save_to_mcontext(), allows the
mcontext argument to be NULL.
- In sendsig_sigcontext(), don't set PSL_VEC in the saved MSR; we can't
actually round-trip the AltiVec registers. At least get them saved
into the PCB by calling vec_save_to_mcontext() (with a NULL mcontext
argument).
- In compat_16_sys___sigreturn14(), call vec_restore_from_mcontext()
with a NULL mcontext argument, which will force any subsequent use
of AltiVec to re-load the AltiVec registers from the PCB.

This isn't ideal, but it's the best we can do with the limited capability
of sigcontext.

Fixes PR port-powerpc/56471.

Drop unused opt_multiprocessor.h includes.

Style and cosmetic changes. No binary changes intended.

allow pcu_save() and pcu_discard() to be called on other threads,
ptrace needs to use it that way.

branches: 1.30.2; 1.30.4;
Don't reload if just re-enabling

branches: 1.29.2; 1.29.4;
pcu(9):
- Remove PCU_KERNEL (hi matt!) and significantly simplify the code.
This experimental feature was tried on ARM did not meet the expectations.
It may be revived one day, but it should be done in a much simpler way.
- Add a message structure for xcall function, pass the LWP ower and thus
optimise a race condition: if LWP is discarding its state on a remote CPU,
but another LWP already did it - do not cause an unecessary re-faulting.
- Reduce the variety of flags for PCU operations (only PCU_VALID and
PCU_REENABLE are used now), pass them only to the pcu_state_load().
- Rename pcu_used_p() to pcu_valid_p(); hopefully it is less confusing.
- pcu_save_all_on_cpu: SPL ought to be used here.
- Update and improve the pcu(9) man page; it needs wizd(8) though.

branches: 1.28.2;
Get rid of MDLWP_USED{FPU,VEC}

-extend the pcu(9) API by a function which saves all context on the
current CPU, and use it if a CPU is taken offline
-add a bool argument to pcu_discard which tells whether the internal
"LWP has used the coprocessor" flag should be set or reset. The flag
is reported by pcu_used_p(). If set, future accesses should use the
state stored in the PCB. If reset, it should be reset to default.
The former case is useful for setmcontext().
With that, it should not be necessary anymore to manage the "FPU used"
state by an additional MD variable.

approved by matt

branches: 1.26.2;
Update to new pcu_state_{load,state,release} definitions

branches: 1.25.2; 1.25.8; 1.25.12;
zero PCU area when loading used area.

branches: 1.24.2;
Set PSL_VEC in the right place.

Make sure to enable the vector unit in the PSL when returning to userland.

Move powerpc to use pcu to manage FPU/AltiVec/SPE.

Powerpc send_ipi use ci_cpuid, not cpu_index

Clear ownership bit after saving contents to PCB.

branches: 1.19.2;
Fix some fallout from building the macppc GENERIC.MP.

Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.17.2;
Retire struct user, remove sys/user.h inclusions. Note sys/user.h header
as obsolete. Remove USER_TO_UAREA/UAREA_TO_USER macros.

Various #include fixes and review by matt@.

branches: 1.16.2;
Adapt to spr.h breakup.

branches: 1.15.2;
Use lwp_getpcb() on mips, powerpc and sh3, clean from struct user usage.

branches: 1.14.4; 1.14.6; 1.14.26;
SMP support for ofppc. (finally) Much thanks to Matt Thomas for help in
figuring out all the crazy nuances of getting this working, and to
Michael Lorenz for testing/fixing my changes on macppc. Tested with a
quad-proc 7044-270.
Summary of changes:

Bumped CPU_MAXNUM to 16 on ofppc.
Added md_* routines to ofppc/cpu.c, to sync the timebase, and awaken the CPUs.
Fixed a bug in the test for a 64bit bridge cpu early in locore.S
Added code to set the interrupt priority for all CPUs with an openpic.
Change rtas to probe before cpus, to allow use of the rtas freeze/thaw
timebase code routines.
Fix CPU_INFO_FOREACH macro to iterate through detected cpus, not CPU_MAXNUM.
Change most uses of ci_cpuid to ci_index, to deal with CPUs that do not allow
writing to SPR_PIR. Don't write SPR_PIR unless the secondary cpu identifies
itself as 0.
Change the hatchstack/interrupt stack allocations to allocate a 8192byte
interrupt stack, and a 4096 byte hatch stack, align them to 16 bytes, and
allocate them no lower than 0x10000. Allocate them separately to prevent the
hatch stack corrupting the interrupt stack later on.
If the CPU is a 64bit cpu, copy SPR_ASR in cpu_hatch()
Set the idle stack to ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_sp.
Add OF_start_cpu(). Add a routine to ofwoea_initppc to spin up secondary
procs early, and place them into a spinloop waiting for the hatch routines
to be ready.
Modify the ipi routines to deal with openpics that reverse byte order on read
from an ipi register. (such as on the 7044)
Change the rtas setup to allocate the rtas physical base address above
the kernel, to avoid mucking up the hatch/interrupt stacks.

branches: 1.13.16;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.12.6; 1.12.14; 1.12.22; 1.12.24; 1.12.26; 1.12.28;
Merge newlock2 to head.

branches: 1.11.20;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

branches: 1.9.2;
Rewrite the inner loop of vcopypage() and vzeropage() to be entirely
in inline asm and include turning the DMMU off and back on. This
prevents the compiler (especially gcc -O0) from inserting accesses to
locations in virtual address space when such accesses would fail.

Don't clear PCB_FPU/PCB_ALTIVEC when releasing the FPU/AltiVec unit. Add
new flags to indicate whether the PCB currently owns the FPU/AltiVec unit.

branches: 1.7.4; 1.7.6;
Add a SAVE/DISCARD flag to save_{fpu,vec}_lwp. Use it appropriately.
Nuke struct fpu and use struct fpreg instead (except for the names, they
were identical). On MP machines, this will avoid an unneeded IPI to save
the register contents that are about to discarded.

Revamp how user MSR/SRR1 are dealt with.
Add a PSL_USEROK_P(psl) macro which valids the bits (replaces the use of
PSL_USERSTATIC).
Add a PSL_USERSRR1 mask which is used to mask out status bits in the upper
half of SRR1.
Make sure PSL_VEC is set appropriately in userret(). PSL_VEC is in the same
region as SSR1 status bits so it's not preserved on exceptions. Thus we
need to make to set it.
When returning a MSR/SRR1 to userland, always clear the status bits.
Add emulation of the mfpvr, mtmsr, and mfmsr instructions.

__KERNEL_RCSID()

branches: 1.4.2;
Make sure to include opt_foo.h if a defflag option FOO is used.

Use PAGE_SIZE rather than NBPG.

Make AltiVec registers available via ptrace/procfs. Simplify AltiVec
processing. Add a "common" procfs_machdep.c for PowerPC platforms.
Even though it is supposed to be port specific, most (if not all)
PowerPC ports can just use the common one.

Rename PPC_MPC6XX to PPC_OEA (and any mpc6xx reference to oea).

- In vec_restore_from_mcontext() and vec_save_to_mcontext(), allows the
mcontext argument to be NULL.
- In sendsig_sigcontext(), don't set PSL_VEC in the saved MSR; we can't
actually round-trip the AltiVec registers. At least get them saved
into the PCB by calling vec_save_to_mcontext() (with a NULL mcontext
argument).
- In compat_16_sys___sigreturn14(), call vec_restore_from_mcontext()
with a NULL mcontext argument, which will force any subsequent use
of AltiVec to re-load the AltiVec registers from the PCB.

This isn't ideal, but it's the best we can do with the limited capability
of sigcontext.

Fixes PR port-powerpc/56471.

Drop unused opt_multiprocessor.h includes.

Style and cosmetic changes. No binary changes intended.

allow pcu_save() and pcu_discard() to be called on other threads,
ptrace needs to use it that way.

branches: 1.30.2; 1.30.4;
Don't reload if just re-enabling

branches: 1.29.2; 1.29.4;
pcu(9):
- Remove PCU_KERNEL (hi matt!) and significantly simplify the code.
This experimental feature was tried on ARM did not meet the expectations.
It may be revived one day, but it should be done in a much simpler way.
- Add a message structure for xcall function, pass the LWP ower and thus
optimise a race condition: if LWP is discarding its state on a remote CPU,
but another LWP already did it - do not cause an unecessary re-faulting.
- Reduce the variety of flags for PCU operations (only PCU_VALID and
PCU_REENABLE are used now), pass them only to the pcu_state_load().
- Rename pcu_used_p() to pcu_valid_p(); hopefully it is less confusing.
- pcu_save_all_on_cpu: SPL ought to be used here.
- Update and improve the pcu(9) man page; it needs wizd(8) though.

branches: 1.28.2;
Get rid of MDLWP_USED{FPU,VEC}

-extend the pcu(9) API by a function which saves all context on the
current CPU, and use it if a CPU is taken offline
-add a bool argument to pcu_discard which tells whether the internal
"LWP has used the coprocessor" flag should be set or reset. The flag
is reported by pcu_used_p(). If set, future accesses should use the
state stored in the PCB. If reset, it should be reset to default.
The former case is useful for setmcontext().
With that, it should not be necessary anymore to manage the "FPU used"
state by an additional MD variable.

approved by matt

branches: 1.26.2;
Update to new pcu_state_{load,state,release} definitions

branches: 1.25.2; 1.25.8; 1.25.12;
zero PCU area when loading used area.

branches: 1.24.2;
Set PSL_VEC in the right place.

Make sure to enable the vector unit in the PSL when returning to userland.

Move powerpc to use pcu to manage FPU/AltiVec/SPE.

Powerpc send_ipi use ci_cpuid, not cpu_index

Clear ownership bit after saving contents to PCB.

branches: 1.19.2;
Fix some fallout from building the macppc GENERIC.MP.

Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.17.2;
Retire struct user, remove sys/user.h inclusions. Note sys/user.h header
as obsolete. Remove USER_TO_UAREA/UAREA_TO_USER macros.

Various #include fixes and review by matt@.

branches: 1.16.2;
Adapt to spr.h breakup.

branches: 1.15.2;
Use lwp_getpcb() on mips, powerpc and sh3, clean from struct user usage.

branches: 1.14.4; 1.14.6; 1.14.26;
SMP support for ofppc. (finally) Much thanks to Matt Thomas for help in
figuring out all the crazy nuances of getting this working, and to
Michael Lorenz for testing/fixing my changes on macppc. Tested with a
quad-proc 7044-270.
Summary of changes:

Bumped CPU_MAXNUM to 16 on ofppc.
Added md_* routines to ofppc/cpu.c, to sync the timebase, and awaken the CPUs.
Fixed a bug in the test for a 64bit bridge cpu early in locore.S
Added code to set the interrupt priority for all CPUs with an openpic.
Change rtas to probe before cpus, to allow use of the rtas freeze/thaw
timebase code routines.
Fix CPU_INFO_FOREACH macro to iterate through detected cpus, not CPU_MAXNUM.
Change most uses of ci_cpuid to ci_index, to deal with CPUs that do not allow
writing to SPR_PIR. Don't write SPR_PIR unless the secondary cpu identifies
itself as 0.
Change the hatchstack/interrupt stack allocations to allocate a 8192byte
interrupt stack, and a 4096 byte hatch stack, align them to 16 bytes, and
allocate them no lower than 0x10000. Allocate them separately to prevent the
hatch stack corrupting the interrupt stack later on.
If the CPU is a 64bit cpu, copy SPR_ASR in cpu_hatch()
Set the idle stack to ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_sp.
Add OF_start_cpu(). Add a routine to ofwoea_initppc to spin up secondary
procs early, and place them into a spinloop waiting for the hatch routines
to be ready.
Modify the ipi routines to deal with openpics that reverse byte order on read
from an ipi register. (such as on the 7044)
Change the rtas setup to allocate the rtas physical base address above
the kernel, to avoid mucking up the hatch/interrupt stacks.

branches: 1.13.16;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.12.6; 1.12.14; 1.12.22; 1.12.24; 1.12.26; 1.12.28;
Merge newlock2 to head.

branches: 1.11.20;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

branches: 1.9.2;
Rewrite the inner loop of vcopypage() and vzeropage() to be entirely
in inline asm and include turning the DMMU off and back on. This
prevents the compiler (especially gcc -O0) from inserting accesses to
locations in virtual address space when such accesses would fail.

Don't clear PCB_FPU/PCB_ALTIVEC when releasing the FPU/AltiVec unit. Add
new flags to indicate whether the PCB currently owns the FPU/AltiVec unit.

branches: 1.7.4; 1.7.6;
Add a SAVE/DISCARD flag to save_{fpu,vec}_lwp. Use it appropriately.
Nuke struct fpu and use struct fpreg instead (except for the names, they
were identical). On MP machines, this will avoid an unneeded IPI to save
the register contents that are about to discarded.

Revamp how user MSR/SRR1 are dealt with.
Add a PSL_USEROK_P(psl) macro which valids the bits (replaces the use of
PSL_USERSTATIC).
Add a PSL_USERSRR1 mask which is used to mask out status bits in the upper
half of SRR1.
Make sure PSL_VEC is set appropriately in userret(). PSL_VEC is in the same
region as SSR1 status bits so it's not preserved on exceptions. Thus we
need to make to set it.
When returning a MSR/SRR1 to userland, always clear the status bits.
Add emulation of the mfpvr, mtmsr, and mfmsr instructions.

__KERNEL_RCSID()

branches: 1.4.2;
Make sure to include opt_foo.h if a defflag option FOO is used.

Use PAGE_SIZE rather than NBPG.

Make AltiVec registers available via ptrace/procfs. Simplify AltiVec
processing. Add a "common" procfs_machdep.c for PowerPC platforms.
Even though it is supposed to be port specific, most (if not all)
PowerPC ports can just use the common one.

Rename PPC_MPC6XX to PPC_OEA (and any mpc6xx reference to oea).

Drop unused opt_multiprocessor.h includes.

Style and cosmetic changes. No binary changes intended.

allow pcu_save() and pcu_discard() to be called on other threads,
ptrace needs to use it that way.

branches: 1.30.2; 1.30.4;
Don't reload if just re-enabling

branches: 1.29.2; 1.29.4;
pcu(9):
- Remove PCU_KERNEL (hi matt!) and significantly simplify the code.
This experimental feature was tried on ARM did not meet the expectations.
It may be revived one day, but it should be done in a much simpler way.
- Add a message structure for xcall function, pass the LWP ower and thus
optimise a race condition: if LWP is discarding its state on a remote CPU,
but another LWP already did it - do not cause an unecessary re-faulting.
- Reduce the variety of flags for PCU operations (only PCU_VALID and
PCU_REENABLE are used now), pass them only to the pcu_state_load().
- Rename pcu_used_p() to pcu_valid_p(); hopefully it is less confusing.
- pcu_save_all_on_cpu: SPL ought to be used here.
- Update and improve the pcu(9) man page; it needs wizd(8) though.

branches: 1.28.2;
Get rid of MDLWP_USED{FPU,VEC}

-extend the pcu(9) API by a function which saves all context on the
current CPU, and use it if a CPU is taken offline
-add a bool argument to pcu_discard which tells whether the internal
"LWP has used the coprocessor" flag should be set or reset. The flag
is reported by pcu_used_p(). If set, future accesses should use the
state stored in the PCB. If reset, it should be reset to default.
The former case is useful for setmcontext().
With that, it should not be necessary anymore to manage the "FPU used"
state by an additional MD variable.

approved by matt

branches: 1.26.2;
Update to new pcu_state_{load,state,release} definitions

branches: 1.25.2; 1.25.8; 1.25.12;
zero PCU area when loading used area.

branches: 1.24.2;
Set PSL_VEC in the right place.

Make sure to enable the vector unit in the PSL when returning to userland.

Move powerpc to use pcu to manage FPU/AltiVec/SPE.

Powerpc send_ipi use ci_cpuid, not cpu_index

Clear ownership bit after saving contents to PCB.

branches: 1.19.2;
Fix some fallout from building the macppc GENERIC.MP.

Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.17.2;
Retire struct user, remove sys/user.h inclusions. Note sys/user.h header
as obsolete. Remove USER_TO_UAREA/UAREA_TO_USER macros.

Various #include fixes and review by matt@.

branches: 1.16.2;
Adapt to spr.h breakup.

branches: 1.15.2;
Use lwp_getpcb() on mips, powerpc and sh3, clean from struct user usage.

branches: 1.14.4; 1.14.6; 1.14.26;
SMP support for ofppc. (finally) Much thanks to Matt Thomas for help in
figuring out all the crazy nuances of getting this working, and to
Michael Lorenz for testing/fixing my changes on macppc. Tested with a
quad-proc 7044-270.
Summary of changes:

Bumped CPU_MAXNUM to 16 on ofppc.
Added md_* routines to ofppc/cpu.c, to sync the timebase, and awaken the CPUs.
Fixed a bug in the test for a 64bit bridge cpu early in locore.S
Added code to set the interrupt priority for all CPUs with an openpic.
Change rtas to probe before cpus, to allow use of the rtas freeze/thaw
timebase code routines.
Fix CPU_INFO_FOREACH macro to iterate through detected cpus, not CPU_MAXNUM.
Change most uses of ci_cpuid to ci_index, to deal with CPUs that do not allow
writing to SPR_PIR. Don't write SPR_PIR unless the secondary cpu identifies
itself as 0.
Change the hatchstack/interrupt stack allocations to allocate a 8192byte
interrupt stack, and a 4096 byte hatch stack, align them to 16 bytes, and
allocate them no lower than 0x10000. Allocate them separately to prevent the
hatch stack corrupting the interrupt stack later on.
If the CPU is a 64bit cpu, copy SPR_ASR in cpu_hatch()
Set the idle stack to ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_sp.
Add OF_start_cpu(). Add a routine to ofwoea_initppc to spin up secondary
procs early, and place them into a spinloop waiting for the hatch routines
to be ready.
Modify the ipi routines to deal with openpics that reverse byte order on read
from an ipi register. (such as on the 7044)
Change the rtas setup to allocate the rtas physical base address above
the kernel, to avoid mucking up the hatch/interrupt stacks.

branches: 1.13.16;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.12.6; 1.12.14; 1.12.22; 1.12.24; 1.12.26; 1.12.28;
Merge newlock2 to head.

branches: 1.11.20;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

branches: 1.9.2;
Rewrite the inner loop of vcopypage() and vzeropage() to be entirely
in inline asm and include turning the DMMU off and back on. This
prevents the compiler (especially gcc -O0) from inserting accesses to
locations in virtual address space when such accesses would fail.

Don't clear PCB_FPU/PCB_ALTIVEC when releasing the FPU/AltiVec unit. Add
new flags to indicate whether the PCB currently owns the FPU/AltiVec unit.

branches: 1.7.4; 1.7.6;
Add a SAVE/DISCARD flag to save_{fpu,vec}_lwp. Use it appropriately.
Nuke struct fpu and use struct fpreg instead (except for the names, they
were identical). On MP machines, this will avoid an unneeded IPI to save
the register contents that are about to discarded.

Revamp how user MSR/SRR1 are dealt with.
Add a PSL_USEROK_P(psl) macro which valids the bits (replaces the use of
PSL_USERSTATIC).
Add a PSL_USERSRR1 mask which is used to mask out status bits in the upper
half of SRR1.
Make sure PSL_VEC is set appropriately in userret(). PSL_VEC is in the same
region as SSR1 status bits so it's not preserved on exceptions. Thus we
need to make to set it.
When returning a MSR/SRR1 to userland, always clear the status bits.
Add emulation of the mfpvr, mtmsr, and mfmsr instructions.

__KERNEL_RCSID()

branches: 1.4.2;
Make sure to include opt_foo.h if a defflag option FOO is used.

Use PAGE_SIZE rather than NBPG.

Make AltiVec registers available via ptrace/procfs. Simplify AltiVec
processing. Add a "common" procfs_machdep.c for PowerPC platforms.
Even though it is supposed to be port specific, most (if not all)
PowerPC ports can just use the common one.

Rename PPC_MPC6XX to PPC_OEA (and any mpc6xx reference to oea).

allow pcu_save() and pcu_discard() to be called on other threads,
ptrace needs to use it that way.

branches: 1.30.2; 1.30.4;
Don't reload if just re-enabling

branches: 1.29.2; 1.29.4;
pcu(9):
- Remove PCU_KERNEL (hi matt!) and significantly simplify the code.
This experimental feature was tried on ARM did not meet the expectations.
It may be revived one day, but it should be done in a much simpler way.
- Add a message structure for xcall function, pass the LWP ower and thus
optimise a race condition: if LWP is discarding its state on a remote CPU,
but another LWP already did it - do not cause an unecessary re-faulting.
- Reduce the variety of flags for PCU operations (only PCU_VALID and
PCU_REENABLE are used now), pass them only to the pcu_state_load().
- Rename pcu_used_p() to pcu_valid_p(); hopefully it is less confusing.
- pcu_save_all_on_cpu: SPL ought to be used here.
- Update and improve the pcu(9) man page; it needs wizd(8) though.

branches: 1.28.2;
Get rid of MDLWP_USED{FPU,VEC}

-extend the pcu(9) API by a function which saves all context on the
current CPU, and use it if a CPU is taken offline
-add a bool argument to pcu_discard which tells whether the internal
"LWP has used the coprocessor" flag should be set or reset. The flag
is reported by pcu_used_p(). If set, future accesses should use the
state stored in the PCB. If reset, it should be reset to default.
The former case is useful for setmcontext().
With that, it should not be necessary anymore to manage the "FPU used"
state by an additional MD variable.

approved by matt

branches: 1.26.2;
Update to new pcu_state_{load,state,release} definitions

branches: 1.25.2; 1.25.8; 1.25.12;
zero PCU area when loading used area.

branches: 1.24.2;
Set PSL_VEC in the right place.

Make sure to enable the vector unit in the PSL when returning to userland.

Move powerpc to use pcu to manage FPU/AltiVec/SPE.

Powerpc send_ipi use ci_cpuid, not cpu_index

Clear ownership bit after saving contents to PCB.

branches: 1.19.2;
Fix some fallout from building the macppc GENERIC.MP.

Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.17.2;
Retire struct user, remove sys/user.h inclusions. Note sys/user.h header
as obsolete. Remove USER_TO_UAREA/UAREA_TO_USER macros.

Various #include fixes and review by matt@.

branches: 1.16.2;
Adapt to spr.h breakup.

branches: 1.15.2;
Use lwp_getpcb() on mips, powerpc and sh3, clean from struct user usage.

branches: 1.14.4; 1.14.6; 1.14.26;
SMP support for ofppc. (finally) Much thanks to Matt Thomas for help in
figuring out all the crazy nuances of getting this working, and to
Michael Lorenz for testing/fixing my changes on macppc. Tested with a
quad-proc 7044-270.
Summary of changes:

Bumped CPU_MAXNUM to 16 on ofppc.
Added md_* routines to ofppc/cpu.c, to sync the timebase, and awaken the CPUs.
Fixed a bug in the test for a 64bit bridge cpu early in locore.S
Added code to set the interrupt priority for all CPUs with an openpic.
Change rtas to probe before cpus, to allow use of the rtas freeze/thaw
timebase code routines.
Fix CPU_INFO_FOREACH macro to iterate through detected cpus, not CPU_MAXNUM.
Change most uses of ci_cpuid to ci_index, to deal with CPUs that do not allow
writing to SPR_PIR. Don't write SPR_PIR unless the secondary cpu identifies
itself as 0.
Change the hatchstack/interrupt stack allocations to allocate a 8192byte
interrupt stack, and a 4096 byte hatch stack, align them to 16 bytes, and
allocate them no lower than 0x10000. Allocate them separately to prevent the
hatch stack corrupting the interrupt stack later on.
If the CPU is a 64bit cpu, copy SPR_ASR in cpu_hatch()
Set the idle stack to ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_sp.
Add OF_start_cpu(). Add a routine to ofwoea_initppc to spin up secondary
procs early, and place them into a spinloop waiting for the hatch routines
to be ready.
Modify the ipi routines to deal with openpics that reverse byte order on read
from an ipi register. (such as on the 7044)
Change the rtas setup to allocate the rtas physical base address above
the kernel, to avoid mucking up the hatch/interrupt stacks.

branches: 1.13.16;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.12.6; 1.12.14; 1.12.22; 1.12.24; 1.12.26; 1.12.28;
Merge newlock2 to head.

branches: 1.11.20;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

branches: 1.9.2;
Rewrite the inner loop of vcopypage() and vzeropage() to be entirely
in inline asm and include turning the DMMU off and back on. This
prevents the compiler (especially gcc -O0) from inserting accesses to
locations in virtual address space when such accesses would fail.

Don't clear PCB_FPU/PCB_ALTIVEC when releasing the FPU/AltiVec unit. Add
new flags to indicate whether the PCB currently owns the FPU/AltiVec unit.

branches: 1.7.4; 1.7.6;
Add a SAVE/DISCARD flag to save_{fpu,vec}_lwp. Use it appropriately.
Nuke struct fpu and use struct fpreg instead (except for the names, they
were identical). On MP machines, this will avoid an unneeded IPI to save
the register contents that are about to discarded.

Revamp how user MSR/SRR1 are dealt with.
Add a PSL_USEROK_P(psl) macro which valids the bits (replaces the use of
PSL_USERSTATIC).
Add a PSL_USERSRR1 mask which is used to mask out status bits in the upper
half of SRR1.
Make sure PSL_VEC is set appropriately in userret(). PSL_VEC is in the same
region as SSR1 status bits so it's not preserved on exceptions. Thus we
need to make to set it.
When returning a MSR/SRR1 to userland, always clear the status bits.
Add emulation of the mfpvr, mtmsr, and mfmsr instructions.

__KERNEL_RCSID()

branches: 1.4.2;
Make sure to include opt_foo.h if a defflag option FOO is used.

Use PAGE_SIZE rather than NBPG.

Make AltiVec registers available via ptrace/procfs. Simplify AltiVec
processing. Add a "common" procfs_machdep.c for PowerPC platforms.
Even though it is supposed to be port specific, most (if not all)
PowerPC ports can just use the common one.

Rename PPC_MPC6XX to PPC_OEA (and any mpc6xx reference to oea).