Stop using deprecated proplib functions.

s/paniced/panicked/ and s/borken/broken/ in comments.

Add missing double p and d for stopped and overriden accordingly.
Fix few more typos along the way, mainly in copy-pasted comments.

Drop unused opt_ddb.h.

Style and cosmetic changes. No binary changes intended.

XXX
Skip KASSERT which fires when !__HAVE_FAST_SOFTINTS. Just for debug.

Do not panic when splraise to IPL_NONE, which is required for
subr_cprng.c rev 1.36 and above:

http://cvsweb.netbsd.org/bsdweb.cgi/src/sys/kern/subr_cprng.c#rev1.36

Fix false sharing problems with cpu_info. Identified with tprof(8).
This was a very nice win in my tests on a 48 CPU box.

- Reorganise cpu_data slightly according to usage.
- Put cpu_onproc into struct cpu_info alongside ci_curlwp (now is ci_onproc).
- On x86, put some items in their own cache lines according to usage, like
the IPI bitmask and ci_want_resched.

cpu_need_resched():

- Remove all code that should be MI, leaving the bare minimum under arch/.
- Make the required actions very explicit.
- Pass in LWP pointer for convenience.
- When a trap is required on another CPU, have the IPI set it locally.
- Expunge cpu_did_resched().

interrupt has two 'r's

fix another typo while I'm here (flsah)

branches: 1.37.2; 1.37.4;
Another try fixing printf format using the ultimate uintmax_t idiom.

fix printf format.

remove checks for failure after memory allocation calls that cannot fail:

kmem_alloc() with KM_SLEEP
kmem_zalloc() with KM_SLEEP
percpu_alloc()
pserialize_create()
psref_class_create()

all of these paths include an assertion that the allocation has not failed,
so callers should not assert that again.

Added MSI/MSI-X and interrupt_distribute(9) support for powerpc.

branches: 1.33.2;
__HAVE_PREEEMPTION -> __HAVE_PREEMPTION

Initialize timer DR.

ddb MP support

Allow to share IPI interrupt.

Initialize lock objects.

Preliminary support for P1023.

Revert previous commit.

Pass ci->ci_cpuid as irq of IST_IPI.
Avoid "panic: e500_intr_cpu_hatch: failed to establish ipi interrupt!" on cpu1.

Added missing mutex_exit() at error path.

branches: 1.24.4;
Implement MI IPI interface with cross-call support.

branches: 1.23.2;
make pci_intr_string and eisa_intr_string take a buffer and a length
instead of relying in local static storage.

branches: 1.22.2;
Change a KASSERT to a KASSERTMSG.

branches: 1.21.2;
Add a machine splhist command to give (a incomplete) spl history.
(only the most recent are going to be accurate).

splraise(6) from 0 at 549214603
splraise(7) from 6 at 549214643 (+40)
splx(6) from 7 at 549214691 (+48)
splx(0) from 6 at 549214730 (+39)

Add two missing interrupt sources for P1025.

Add support for the Freescale TWR-P1025 evaluation board and the P1025/P1016
QorIQ processors. XXX tsec isn't working yet on the TWR-P1025.

If we paniced because a watchdog timed out, PSL_CE will be clear. So don't
assert PSL_CE is set if panicstr is not NULL.

Compute softintr mask correctly.

branches: 1.16.2; 1.16.8;
Modify *ASSERTMSG() so they are now used as variadic macros. The main goal
is to provide routines that do as KASSERT(9) says: append a message
to the panic format string when the assertion triggers, with optional
arguments.

Fix call sites to reflect the new definition.

Discussed on tech-kern@. See
http://mail-index.netbsd.org/tech-kern/2011/09/07/msg011427.html

Add missing $NetBSD$ and/or __KERNEL_RCSID.

Panic when an ipi is sent to unknown cpu.

Make powerpc work on BookE. At this time we only support DOZE (lightest
form of power-saving). By default, power-saving is disabled but can be
enabled in /etc/sysctl.conf by setting machdep.powersave=1

In e500_spl0, grab ci after disabling interrupts.
Consolidate a KASSERT.

Add IST_PULSE and intr_typename (converts IST_* to a name).

Take the fast softint support in e500_intr.c and make generic so that it can
be used to provide fast softint for other interrupt implementations.

Add an e500_idlespin to detect calls to idlespin when interrupts are blocked
or disabled.

Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

branches: 1.7.2;
Remove debugging printf. Add missing IMU2 interrupt string.

Add some grotty #ifdef'age to make this compile w/o DIAGNOSTIC.

Fix a bug in onchip_intr_name_lookup

Fix various nits related to P2020 support.

branches: 1.3.2;
Cleanup intr_info initialization. Make it per SVR.

branches: 1.2.2;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.1.2; 1.1.4;
file e500_intr.c was initially added on branch matt-nb5-pq3.

s/paniced/panicked/ and s/borken/broken/ in comments.

Add missing double p and d for stopped and overriden accordingly.
Fix few more typos along the way, mainly in copy-pasted comments.

Drop unused opt_ddb.h.

Style and cosmetic changes. No binary changes intended.

XXX
Skip KASSERT which fires when !__HAVE_FAST_SOFTINTS. Just for debug.

Do not panic when splraise to IPL_NONE, which is required for
subr_cprng.c rev 1.36 and above:

http://cvsweb.netbsd.org/bsdweb.cgi/src/sys/kern/subr_cprng.c#rev1.36

Fix false sharing problems with cpu_info. Identified with tprof(8).
This was a very nice win in my tests on a 48 CPU box.

- Reorganise cpu_data slightly according to usage.
- Put cpu_onproc into struct cpu_info alongside ci_curlwp (now is ci_onproc).
- On x86, put some items in their own cache lines according to usage, like
the IPI bitmask and ci_want_resched.

cpu_need_resched():

- Remove all code that should be MI, leaving the bare minimum under arch/.
- Make the required actions very explicit.
- Pass in LWP pointer for convenience.
- When a trap is required on another CPU, have the IPI set it locally.
- Expunge cpu_did_resched().

interrupt has two 'r's

fix another typo while I'm here (flsah)

branches: 1.37.2; 1.37.4;
Another try fixing printf format using the ultimate uintmax_t idiom.

fix printf format.

remove checks for failure after memory allocation calls that cannot fail:

kmem_alloc() with KM_SLEEP
kmem_zalloc() with KM_SLEEP
percpu_alloc()
pserialize_create()
psref_class_create()

all of these paths include an assertion that the allocation has not failed,
so callers should not assert that again.

Added MSI/MSI-X and interrupt_distribute(9) support for powerpc.

branches: 1.33.2;
__HAVE_PREEEMPTION -> __HAVE_PREEMPTION

Initialize timer DR.

ddb MP support

Allow to share IPI interrupt.

Initialize lock objects.

Preliminary support for P1023.

Revert previous commit.

Pass ci->ci_cpuid as irq of IST_IPI.
Avoid "panic: e500_intr_cpu_hatch: failed to establish ipi interrupt!" on cpu1.

Added missing mutex_exit() at error path.

branches: 1.24.4;
Implement MI IPI interface with cross-call support.

branches: 1.23.2;
make pci_intr_string and eisa_intr_string take a buffer and a length
instead of relying in local static storage.

branches: 1.22.2;
Change a KASSERT to a KASSERTMSG.

branches: 1.21.2;
Add a machine splhist command to give (a incomplete) spl history.
(only the most recent are going to be accurate).

splraise(6) from 0 at 549214603
splraise(7) from 6 at 549214643 (+40)
splx(6) from 7 at 549214691 (+48)
splx(0) from 6 at 549214730 (+39)

Add two missing interrupt sources for P1025.

Add support for the Freescale TWR-P1025 evaluation board and the P1025/P1016
QorIQ processors. XXX tsec isn't working yet on the TWR-P1025.

If we paniced because a watchdog timed out, PSL_CE will be clear. So don't
assert PSL_CE is set if panicstr is not NULL.

Compute softintr mask correctly.

branches: 1.16.2; 1.16.8;
Modify *ASSERTMSG() so they are now used as variadic macros. The main goal
is to provide routines that do as KASSERT(9) says: append a message
to the panic format string when the assertion triggers, with optional
arguments.

Fix call sites to reflect the new definition.

Discussed on tech-kern@. See
http://mail-index.netbsd.org/tech-kern/2011/09/07/msg011427.html

Add missing $NetBSD$ and/or __KERNEL_RCSID.

Panic when an ipi is sent to unknown cpu.

Make powerpc work on BookE. At this time we only support DOZE (lightest
form of power-saving). By default, power-saving is disabled but can be
enabled in /etc/sysctl.conf by setting machdep.powersave=1

In e500_spl0, grab ci after disabling interrupts.
Consolidate a KASSERT.

Add IST_PULSE and intr_typename (converts IST_* to a name).

Take the fast softint support in e500_intr.c and make generic so that it can
be used to provide fast softint for other interrupt implementations.

Add an e500_idlespin to detect calls to idlespin when interrupts are blocked
or disabled.

Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

branches: 1.7.2;
Remove debugging printf. Add missing IMU2 interrupt string.

Add some grotty #ifdef'age to make this compile w/o DIAGNOSTIC.

Fix a bug in onchip_intr_name_lookup

Fix various nits related to P2020 support.

branches: 1.3.2;
Cleanup intr_info initialization. Make it per SVR.

branches: 1.2.2;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.1.2; 1.1.4;
file e500_intr.c was initially added on branch matt-nb5-pq3.

Add missing double p and d for stopped and overriden accordingly.
Fix few more typos along the way, mainly in copy-pasted comments.

Drop unused opt_ddb.h.

Style and cosmetic changes. No binary changes intended.

XXX
Skip KASSERT which fires when !__HAVE_FAST_SOFTINTS. Just for debug.

Do not panic when splraise to IPL_NONE, which is required for
subr_cprng.c rev 1.36 and above:

http://cvsweb.netbsd.org/bsdweb.cgi/src/sys/kern/subr_cprng.c#rev1.36

Fix false sharing problems with cpu_info. Identified with tprof(8).
This was a very nice win in my tests on a 48 CPU box.

- Reorganise cpu_data slightly according to usage.
- Put cpu_onproc into struct cpu_info alongside ci_curlwp (now is ci_onproc).
- On x86, put some items in their own cache lines according to usage, like
the IPI bitmask and ci_want_resched.

cpu_need_resched():

- Remove all code that should be MI, leaving the bare minimum under arch/.
- Make the required actions very explicit.
- Pass in LWP pointer for convenience.
- When a trap is required on another CPU, have the IPI set it locally.
- Expunge cpu_did_resched().

interrupt has two 'r's

fix another typo while I'm here (flsah)

branches: 1.37.2; 1.37.4;
Another try fixing printf format using the ultimate uintmax_t idiom.

fix printf format.

remove checks for failure after memory allocation calls that cannot fail:

kmem_alloc() with KM_SLEEP
kmem_zalloc() with KM_SLEEP
percpu_alloc()
pserialize_create()
psref_class_create()

all of these paths include an assertion that the allocation has not failed,
so callers should not assert that again.

Added MSI/MSI-X and interrupt_distribute(9) support for powerpc.

branches: 1.33.2;
__HAVE_PREEEMPTION -> __HAVE_PREEMPTION

Initialize timer DR.

ddb MP support

Allow to share IPI interrupt.

Initialize lock objects.

Preliminary support for P1023.

Revert previous commit.

Pass ci->ci_cpuid as irq of IST_IPI.
Avoid "panic: e500_intr_cpu_hatch: failed to establish ipi interrupt!" on cpu1.

Added missing mutex_exit() at error path.

branches: 1.24.4;
Implement MI IPI interface with cross-call support.

branches: 1.23.2;
make pci_intr_string and eisa_intr_string take a buffer and a length
instead of relying in local static storage.

branches: 1.22.2;
Change a KASSERT to a KASSERTMSG.

branches: 1.21.2;
Add a machine splhist command to give (a incomplete) spl history.
(only the most recent are going to be accurate).

splraise(6) from 0 at 549214603
splraise(7) from 6 at 549214643 (+40)
splx(6) from 7 at 549214691 (+48)
splx(0) from 6 at 549214730 (+39)

Add two missing interrupt sources for P1025.

Add support for the Freescale TWR-P1025 evaluation board and the P1025/P1016
QorIQ processors. XXX tsec isn't working yet on the TWR-P1025.

If we paniced because a watchdog timed out, PSL_CE will be clear. So don't
assert PSL_CE is set if panicstr is not NULL.

Compute softintr mask correctly.

branches: 1.16.2; 1.16.8;
Modify *ASSERTMSG() so they are now used as variadic macros. The main goal
is to provide routines that do as KASSERT(9) says: append a message
to the panic format string when the assertion triggers, with optional
arguments.

Fix call sites to reflect the new definition.

Discussed on tech-kern@. See
http://mail-index.netbsd.org/tech-kern/2011/09/07/msg011427.html

Add missing $NetBSD$ and/or __KERNEL_RCSID.

Panic when an ipi is sent to unknown cpu.

Make powerpc work on BookE. At this time we only support DOZE (lightest
form of power-saving). By default, power-saving is disabled but can be
enabled in /etc/sysctl.conf by setting machdep.powersave=1

In e500_spl0, grab ci after disabling interrupts.
Consolidate a KASSERT.

Add IST_PULSE and intr_typename (converts IST_* to a name).

Take the fast softint support in e500_intr.c and make generic so that it can
be used to provide fast softint for other interrupt implementations.

Add an e500_idlespin to detect calls to idlespin when interrupts are blocked
or disabled.

Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

branches: 1.7.2;
Remove debugging printf. Add missing IMU2 interrupt string.

Add some grotty #ifdef'age to make this compile w/o DIAGNOSTIC.

Fix a bug in onchip_intr_name_lookup

Fix various nits related to P2020 support.

branches: 1.3.2;
Cleanup intr_info initialization. Make it per SVR.

branches: 1.2.2;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.1.2; 1.1.4;
file e500_intr.c was initially added on branch matt-nb5-pq3.

Drop unused opt_ddb.h.

Style and cosmetic changes. No binary changes intended.

XXX
Skip KASSERT which fires when !__HAVE_FAST_SOFTINTS. Just for debug.

Do not panic when splraise to IPL_NONE, which is required for
subr_cprng.c rev 1.36 and above:

http://cvsweb.netbsd.org/bsdweb.cgi/src/sys/kern/subr_cprng.c#rev1.36

Fix false sharing problems with cpu_info. Identified with tprof(8).
This was a very nice win in my tests on a 48 CPU box.

- Reorganise cpu_data slightly according to usage.
- Put cpu_onproc into struct cpu_info alongside ci_curlwp (now is ci_onproc).
- On x86, put some items in their own cache lines according to usage, like
the IPI bitmask and ci_want_resched.

cpu_need_resched():

- Remove all code that should be MI, leaving the bare minimum under arch/.
- Make the required actions very explicit.
- Pass in LWP pointer for convenience.
- When a trap is required on another CPU, have the IPI set it locally.
- Expunge cpu_did_resched().

interrupt has two 'r's

fix another typo while I'm here (flsah)

branches: 1.37.2; 1.37.4;
Another try fixing printf format using the ultimate uintmax_t idiom.

fix printf format.

remove checks for failure after memory allocation calls that cannot fail:

kmem_alloc() with KM_SLEEP
kmem_zalloc() with KM_SLEEP
percpu_alloc()
pserialize_create()
psref_class_create()

all of these paths include an assertion that the allocation has not failed,
so callers should not assert that again.

Added MSI/MSI-X and interrupt_distribute(9) support for powerpc.

branches: 1.33.2;
__HAVE_PREEEMPTION -> __HAVE_PREEMPTION

Initialize timer DR.

ddb MP support

Allow to share IPI interrupt.

Initialize lock objects.

Preliminary support for P1023.

Revert previous commit.

Pass ci->ci_cpuid as irq of IST_IPI.
Avoid "panic: e500_intr_cpu_hatch: failed to establish ipi interrupt!" on cpu1.

Added missing mutex_exit() at error path.

branches: 1.24.4;
Implement MI IPI interface with cross-call support.

branches: 1.23.2;
make pci_intr_string and eisa_intr_string take a buffer and a length
instead of relying in local static storage.

branches: 1.22.2;
Change a KASSERT to a KASSERTMSG.

branches: 1.21.2;
Add a machine splhist command to give (a incomplete) spl history.
(only the most recent are going to be accurate).

splraise(6) from 0 at 549214603
splraise(7) from 6 at 549214643 (+40)
splx(6) from 7 at 549214691 (+48)
splx(0) from 6 at 549214730 (+39)

Add two missing interrupt sources for P1025.

Add support for the Freescale TWR-P1025 evaluation board and the P1025/P1016
QorIQ processors. XXX tsec isn't working yet on the TWR-P1025.

If we paniced because a watchdog timed out, PSL_CE will be clear. So don't
assert PSL_CE is set if panicstr is not NULL.

Compute softintr mask correctly.

branches: 1.16.2; 1.16.8;
Modify *ASSERTMSG() so they are now used as variadic macros. The main goal
is to provide routines that do as KASSERT(9) says: append a message
to the panic format string when the assertion triggers, with optional
arguments.

Fix call sites to reflect the new definition.

Discussed on tech-kern@. See
http://mail-index.netbsd.org/tech-kern/2011/09/07/msg011427.html

Add missing $NetBSD$ and/or __KERNEL_RCSID.

Panic when an ipi is sent to unknown cpu.

Make powerpc work on BookE. At this time we only support DOZE (lightest
form of power-saving). By default, power-saving is disabled but can be
enabled in /etc/sysctl.conf by setting machdep.powersave=1

In e500_spl0, grab ci after disabling interrupts.
Consolidate a KASSERT.

Add IST_PULSE and intr_typename (converts IST_* to a name).

Take the fast softint support in e500_intr.c and make generic so that it can
be used to provide fast softint for other interrupt implementations.

Add an e500_idlespin to detect calls to idlespin when interrupts are blocked
or disabled.

Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

branches: 1.7.2;
Remove debugging printf. Add missing IMU2 interrupt string.

Add some grotty #ifdef'age to make this compile w/o DIAGNOSTIC.

Fix a bug in onchip_intr_name_lookup

Fix various nits related to P2020 support.

branches: 1.3.2;
Cleanup intr_info initialization. Make it per SVR.

branches: 1.2.2;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.1.2; 1.1.4;
file e500_intr.c was initially added on branch matt-nb5-pq3.

Do not panic when splraise to IPL_NONE, which is required for
subr_cprng.c rev 1.36 and above:

http://cvsweb.netbsd.org/bsdweb.cgi/src/sys/kern/subr_cprng.c#rev1.36

Fix false sharing problems with cpu_info. Identified with tprof(8).
This was a very nice win in my tests on a 48 CPU box.

- Reorganise cpu_data slightly according to usage.
- Put cpu_onproc into struct cpu_info alongside ci_curlwp (now is ci_onproc).
- On x86, put some items in their own cache lines according to usage, like
the IPI bitmask and ci_want_resched.

cpu_need_resched():

- Remove all code that should be MI, leaving the bare minimum under arch/.
- Make the required actions very explicit.
- Pass in LWP pointer for convenience.
- When a trap is required on another CPU, have the IPI set it locally.
- Expunge cpu_did_resched().

interrupt has two 'r's

fix another typo while I'm here (flsah)

branches: 1.37.2; 1.37.4;
Another try fixing printf format using the ultimate uintmax_t idiom.

fix printf format.

remove checks for failure after memory allocation calls that cannot fail:

kmem_alloc() with KM_SLEEP
kmem_zalloc() with KM_SLEEP
percpu_alloc()
pserialize_create()
psref_class_create()

all of these paths include an assertion that the allocation has not failed,
so callers should not assert that again.

Added MSI/MSI-X and interrupt_distribute(9) support for powerpc.

branches: 1.33.2;
__HAVE_PREEEMPTION -> __HAVE_PREEMPTION

Initialize timer DR.

ddb MP support

Allow to share IPI interrupt.

Initialize lock objects.

Preliminary support for P1023.

Revert previous commit.

Pass ci->ci_cpuid as irq of IST_IPI.
Avoid "panic: e500_intr_cpu_hatch: failed to establish ipi interrupt!" on cpu1.

Added missing mutex_exit() at error path.

branches: 1.24.4;
Implement MI IPI interface with cross-call support.

branches: 1.23.2;
make pci_intr_string and eisa_intr_string take a buffer and a length
instead of relying in local static storage.

branches: 1.22.2;
Change a KASSERT to a KASSERTMSG.

branches: 1.21.2;
Add a machine splhist command to give (a incomplete) spl history.
(only the most recent are going to be accurate).

splraise(6) from 0 at 549214603
splraise(7) from 6 at 549214643 (+40)
splx(6) from 7 at 549214691 (+48)
splx(0) from 6 at 549214730 (+39)

Add two missing interrupt sources for P1025.

Add support for the Freescale TWR-P1025 evaluation board and the P1025/P1016
QorIQ processors. XXX tsec isn't working yet on the TWR-P1025.

If we paniced because a watchdog timed out, PSL_CE will be clear. So don't
assert PSL_CE is set if panicstr is not NULL.

Compute softintr mask correctly.

branches: 1.16.2; 1.16.8;
Modify *ASSERTMSG() so they are now used as variadic macros. The main goal
is to provide routines that do as KASSERT(9) says: append a message
to the panic format string when the assertion triggers, with optional
arguments.

Fix call sites to reflect the new definition.

Discussed on tech-kern@. See
http://mail-index.netbsd.org/tech-kern/2011/09/07/msg011427.html

Add missing $NetBSD$ and/or __KERNEL_RCSID.

Panic when an ipi is sent to unknown cpu.

Make powerpc work on BookE. At this time we only support DOZE (lightest
form of power-saving). By default, power-saving is disabled but can be
enabled in /etc/sysctl.conf by setting machdep.powersave=1

In e500_spl0, grab ci after disabling interrupts.
Consolidate a KASSERT.

Add IST_PULSE and intr_typename (converts IST_* to a name).

Take the fast softint support in e500_intr.c and make generic so that it can
be used to provide fast softint for other interrupt implementations.

Add an e500_idlespin to detect calls to idlespin when interrupts are blocked
or disabled.

Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

branches: 1.7.2;
Remove debugging printf. Add missing IMU2 interrupt string.

Add some grotty #ifdef'age to make this compile w/o DIAGNOSTIC.

Fix a bug in onchip_intr_name_lookup

Fix various nits related to P2020 support.

branches: 1.3.2;
Cleanup intr_info initialization. Make it per SVR.

branches: 1.2.2;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.1.2; 1.1.4;
file e500_intr.c was initially added on branch matt-nb5-pq3.

Fix false sharing problems with cpu_info. Identified with tprof(8).
This was a very nice win in my tests on a 48 CPU box.

- Reorganise cpu_data slightly according to usage.
- Put cpu_onproc into struct cpu_info alongside ci_curlwp (now is ci_onproc).
- On x86, put some items in their own cache lines according to usage, like
the IPI bitmask and ci_want_resched.

cpu_need_resched():

- Remove all code that should be MI, leaving the bare minimum under arch/.
- Make the required actions very explicit.
- Pass in LWP pointer for convenience.
- When a trap is required on another CPU, have the IPI set it locally.
- Expunge cpu_did_resched().

interrupt has two 'r's

fix another typo while I'm here (flsah)

branches: 1.37.2; 1.37.4;
Another try fixing printf format using the ultimate uintmax_t idiom.

fix printf format.

remove checks for failure after memory allocation calls that cannot fail:

kmem_alloc() with KM_SLEEP
kmem_zalloc() with KM_SLEEP
percpu_alloc()
pserialize_create()
psref_class_create()

all of these paths include an assertion that the allocation has not failed,
so callers should not assert that again.

Added MSI/MSI-X and interrupt_distribute(9) support for powerpc.

branches: 1.33.2;
__HAVE_PREEEMPTION -> __HAVE_PREEMPTION

Initialize timer DR.

ddb MP support

Allow to share IPI interrupt.

Initialize lock objects.

Preliminary support for P1023.

Revert previous commit.

Pass ci->ci_cpuid as irq of IST_IPI.
Avoid "panic: e500_intr_cpu_hatch: failed to establish ipi interrupt!" on cpu1.

Added missing mutex_exit() at error path.

branches: 1.24.4;
Implement MI IPI interface with cross-call support.

branches: 1.23.2;
make pci_intr_string and eisa_intr_string take a buffer and a length
instead of relying in local static storage.

branches: 1.22.2;
Change a KASSERT to a KASSERTMSG.

branches: 1.21.2;
Add a machine splhist command to give (a incomplete) spl history.
(only the most recent are going to be accurate).

splraise(6) from 0 at 549214603
splraise(7) from 6 at 549214643 (+40)
splx(6) from 7 at 549214691 (+48)
splx(0) from 6 at 549214730 (+39)

Add two missing interrupt sources for P1025.

Add support for the Freescale TWR-P1025 evaluation board and the P1025/P1016
QorIQ processors. XXX tsec isn't working yet on the TWR-P1025.

If we paniced because a watchdog timed out, PSL_CE will be clear. So don't
assert PSL_CE is set if panicstr is not NULL.

Compute softintr mask correctly.

branches: 1.16.2; 1.16.8;
Modify *ASSERTMSG() so they are now used as variadic macros. The main goal
is to provide routines that do as KASSERT(9) says: append a message
to the panic format string when the assertion triggers, with optional
arguments.

Fix call sites to reflect the new definition.

Discussed on tech-kern@. See
http://mail-index.netbsd.org/tech-kern/2011/09/07/msg011427.html

Add missing $NetBSD$ and/or __KERNEL_RCSID.

Panic when an ipi is sent to unknown cpu.

Make powerpc work on BookE. At this time we only support DOZE (lightest
form of power-saving). By default, power-saving is disabled but can be
enabled in /etc/sysctl.conf by setting machdep.powersave=1

In e500_spl0, grab ci after disabling interrupts.
Consolidate a KASSERT.

Add IST_PULSE and intr_typename (converts IST_* to a name).

Take the fast softint support in e500_intr.c and make generic so that it can
be used to provide fast softint for other interrupt implementations.

Add an e500_idlespin to detect calls to idlespin when interrupts are blocked
or disabled.

Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

branches: 1.7.2;
Remove debugging printf. Add missing IMU2 interrupt string.

Add some grotty #ifdef'age to make this compile w/o DIAGNOSTIC.

Fix a bug in onchip_intr_name_lookup

Fix various nits related to P2020 support.

branches: 1.3.2;
Cleanup intr_info initialization. Make it per SVR.

branches: 1.2.2;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.1.2; 1.1.4;
file e500_intr.c was initially added on branch matt-nb5-pq3.

cpu_need_resched():

- Remove all code that should be MI, leaving the bare minimum under arch/.
- Make the required actions very explicit.
- Pass in LWP pointer for convenience.
- When a trap is required on another CPU, have the IPI set it locally.
- Expunge cpu_did_resched().

interrupt has two 'r's

fix another typo while I'm here (flsah)

branches: 1.37.2; 1.37.4;
Another try fixing printf format using the ultimate uintmax_t idiom.

fix printf format.

remove checks for failure after memory allocation calls that cannot fail:

kmem_alloc() with KM_SLEEP
kmem_zalloc() with KM_SLEEP
percpu_alloc()
pserialize_create()
psref_class_create()

all of these paths include an assertion that the allocation has not failed,
so callers should not assert that again.

Added MSI/MSI-X and interrupt_distribute(9) support for powerpc.

branches: 1.33.2;
__HAVE_PREEEMPTION -> __HAVE_PREEMPTION

Initialize timer DR.

ddb MP support

Allow to share IPI interrupt.

Initialize lock objects.

Preliminary support for P1023.

Revert previous commit.

Pass ci->ci_cpuid as irq of IST_IPI.
Avoid "panic: e500_intr_cpu_hatch: failed to establish ipi interrupt!" on cpu1.

Added missing mutex_exit() at error path.

branches: 1.24.4;
Implement MI IPI interface with cross-call support.

branches: 1.23.2;
make pci_intr_string and eisa_intr_string take a buffer and a length
instead of relying in local static storage.

branches: 1.22.2;
Change a KASSERT to a KASSERTMSG.

branches: 1.21.2;
Add a machine splhist command to give (a incomplete) spl history.
(only the most recent are going to be accurate).

splraise(6) from 0 at 549214603
splraise(7) from 6 at 549214643 (+40)
splx(6) from 7 at 549214691 (+48)
splx(0) from 6 at 549214730 (+39)

Add two missing interrupt sources for P1025.

Add support for the Freescale TWR-P1025 evaluation board and the P1025/P1016
QorIQ processors. XXX tsec isn't working yet on the TWR-P1025.

If we paniced because a watchdog timed out, PSL_CE will be clear. So don't
assert PSL_CE is set if panicstr is not NULL.

Compute softintr mask correctly.

branches: 1.16.2; 1.16.8;
Modify *ASSERTMSG() so they are now used as variadic macros. The main goal
is to provide routines that do as KASSERT(9) says: append a message
to the panic format string when the assertion triggers, with optional
arguments.

Fix call sites to reflect the new definition.

Discussed on tech-kern@. See
http://mail-index.netbsd.org/tech-kern/2011/09/07/msg011427.html

Add missing $NetBSD$ and/or __KERNEL_RCSID.

Panic when an ipi is sent to unknown cpu.

Make powerpc work on BookE. At this time we only support DOZE (lightest
form of power-saving). By default, power-saving is disabled but can be
enabled in /etc/sysctl.conf by setting machdep.powersave=1

In e500_spl0, grab ci after disabling interrupts.
Consolidate a KASSERT.

Add IST_PULSE and intr_typename (converts IST_* to a name).

Take the fast softint support in e500_intr.c and make generic so that it can
be used to provide fast softint for other interrupt implementations.

Add an e500_idlespin to detect calls to idlespin when interrupts are blocked
or disabled.

Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

branches: 1.7.2;
Remove debugging printf. Add missing IMU2 interrupt string.

Add some grotty #ifdef'age to make this compile w/o DIAGNOSTIC.

Fix a bug in onchip_intr_name_lookup

Fix various nits related to P2020 support.

branches: 1.3.2;
Cleanup intr_info initialization. Make it per SVR.

branches: 1.2.2;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.1.2; 1.1.4;
file e500_intr.c was initially added on branch matt-nb5-pq3.

interrupt has two 'r's

fix another typo while I'm here (flsah)

branches: 1.37.2;
Another try fixing printf format using the ultimate uintmax_t idiom.

fix printf format.

remove checks for failure after memory allocation calls that cannot fail:

kmem_alloc() with KM_SLEEP
kmem_zalloc() with KM_SLEEP
percpu_alloc()
pserialize_create()
psref_class_create()

all of these paths include an assertion that the allocation has not failed,
so callers should not assert that again.

Added MSI/MSI-X and interrupt_distribute(9) support for powerpc.

branches: 1.33.2;
__HAVE_PREEEMPTION -> __HAVE_PREEMPTION

Initialize timer DR.

ddb MP support

Allow to share IPI interrupt.

Initialize lock objects.

Preliminary support for P1023.

Revert previous commit.

Pass ci->ci_cpuid as irq of IST_IPI.
Avoid "panic: e500_intr_cpu_hatch: failed to establish ipi interrupt!" on cpu1.

Added missing mutex_exit() at error path.

branches: 1.24.4;
Implement MI IPI interface with cross-call support.

branches: 1.23.2;
make pci_intr_string and eisa_intr_string take a buffer and a length
instead of relying in local static storage.

branches: 1.22.2;
Change a KASSERT to a KASSERTMSG.

branches: 1.21.2;
Add a machine splhist command to give (a incomplete) spl history.
(only the most recent are going to be accurate).

splraise(6) from 0 at 549214603
splraise(7) from 6 at 549214643 (+40)
splx(6) from 7 at 549214691 (+48)
splx(0) from 6 at 549214730 (+39)

Add two missing interrupt sources for P1025.

Add support for the Freescale TWR-P1025 evaluation board and the P1025/P1016
QorIQ processors. XXX tsec isn't working yet on the TWR-P1025.

If we paniced because a watchdog timed out, PSL_CE will be clear. So don't
assert PSL_CE is set if panicstr is not NULL.

Compute softintr mask correctly.

branches: 1.16.2; 1.16.8;
Modify *ASSERTMSG() so they are now used as variadic macros. The main goal
is to provide routines that do as KASSERT(9) says: append a message
to the panic format string when the assertion triggers, with optional
arguments.

Fix call sites to reflect the new definition.

Discussed on tech-kern@. See
http://mail-index.netbsd.org/tech-kern/2011/09/07/msg011427.html

Add missing $NetBSD$ and/or __KERNEL_RCSID.

Panic when an ipi is sent to unknown cpu.

Make powerpc work on BookE. At this time we only support DOZE (lightest
form of power-saving). By default, power-saving is disabled but can be
enabled in /etc/sysctl.conf by setting machdep.powersave=1

In e500_spl0, grab ci after disabling interrupts.
Consolidate a KASSERT.

Add IST_PULSE and intr_typename (converts IST_* to a name).

Take the fast softint support in e500_intr.c and make generic so that it can
be used to provide fast softint for other interrupt implementations.

Add an e500_idlespin to detect calls to idlespin when interrupts are blocked
or disabled.

Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

branches: 1.7.2;
Remove debugging printf. Add missing IMU2 interrupt string.

Add some grotty #ifdef'age to make this compile w/o DIAGNOSTIC.

Fix a bug in onchip_intr_name_lookup

Fix various nits related to P2020 support.

branches: 1.3.2;
Cleanup intr_info initialization. Make it per SVR.

branches: 1.2.2;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.1.2; 1.1.4;
file e500_intr.c was initially added on branch matt-nb5-pq3.

Another try fixing printf format using the ultimate uintmax_t idiom.

fix printf format.

remove checks for failure after memory allocation calls that cannot fail:

kmem_alloc() with KM_SLEEP
kmem_zalloc() with KM_SLEEP
percpu_alloc()
pserialize_create()
psref_class_create()

all of these paths include an assertion that the allocation has not failed,
so callers should not assert that again.

Added MSI/MSI-X and interrupt_distribute(9) support for powerpc.

branches: 1.33.2;
__HAVE_PREEEMPTION -> __HAVE_PREEMPTION

Initialize timer DR.

ddb MP support

Allow to share IPI interrupt.

Initialize lock objects.

Preliminary support for P1023.

Revert previous commit.

Pass ci->ci_cpuid as irq of IST_IPI.
Avoid "panic: e500_intr_cpu_hatch: failed to establish ipi interrupt!" on cpu1.

Added missing mutex_exit() at error path.

branches: 1.24.4;
Implement MI IPI interface with cross-call support.

branches: 1.23.2;
make pci_intr_string and eisa_intr_string take a buffer and a length
instead of relying in local static storage.

branches: 1.22.2;
Change a KASSERT to a KASSERTMSG.

branches: 1.21.2;
Add a machine splhist command to give (a incomplete) spl history.
(only the most recent are going to be accurate).

splraise(6) from 0 at 549214603
splraise(7) from 6 at 549214643 (+40)
splx(6) from 7 at 549214691 (+48)
splx(0) from 6 at 549214730 (+39)

Add two missing interrupt sources for P1025.

Add support for the Freescale TWR-P1025 evaluation board and the P1025/P1016
QorIQ processors. XXX tsec isn't working yet on the TWR-P1025.

If we paniced because a watchdog timed out, PSL_CE will be clear. So don't
assert PSL_CE is set if panicstr is not NULL.

Compute softintr mask correctly.

branches: 1.16.2; 1.16.8;
Modify *ASSERTMSG() so they are now used as variadic macros. The main goal
is to provide routines that do as KASSERT(9) says: append a message
to the panic format string when the assertion triggers, with optional
arguments.

Fix call sites to reflect the new definition.

Discussed on tech-kern@. See
http://mail-index.netbsd.org/tech-kern/2011/09/07/msg011427.html

Add missing $NetBSD$ and/or __KERNEL_RCSID.

Panic when an ipi is sent to unknown cpu.

Make powerpc work on BookE. At this time we only support DOZE (lightest
form of power-saving). By default, power-saving is disabled but can be
enabled in /etc/sysctl.conf by setting machdep.powersave=1

In e500_spl0, grab ci after disabling interrupts.
Consolidate a KASSERT.

Add IST_PULSE and intr_typename (converts IST_* to a name).

Take the fast softint support in e500_intr.c and make generic so that it can
be used to provide fast softint for other interrupt implementations.

Add an e500_idlespin to detect calls to idlespin when interrupts are blocked
or disabled.

Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

branches: 1.7.2;
Remove debugging printf. Add missing IMU2 interrupt string.

Add some grotty #ifdef'age to make this compile w/o DIAGNOSTIC.

Fix a bug in onchip_intr_name_lookup

Fix various nits related to P2020 support.

branches: 1.3.2;
Cleanup intr_info initialization. Make it per SVR.

branches: 1.2.2;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.1.2; 1.1.4;
file e500_intr.c was initially added on branch matt-nb5-pq3.

fix printf format.

remove checks for failure after memory allocation calls that cannot fail:

kmem_alloc() with KM_SLEEP
kmem_zalloc() with KM_SLEEP
percpu_alloc()
pserialize_create()
psref_class_create()

all of these paths include an assertion that the allocation has not failed,
so callers should not assert that again.

Added MSI/MSI-X and interrupt_distribute(9) support for powerpc.

branches: 1.33.2;
__HAVE_PREEEMPTION -> __HAVE_PREEMPTION

Initialize timer DR.

ddb MP support

Allow to share IPI interrupt.

Initialize lock objects.

Preliminary support for P1023.

Revert previous commit.

Pass ci->ci_cpuid as irq of IST_IPI.
Avoid "panic: e500_intr_cpu_hatch: failed to establish ipi interrupt!" on cpu1.

Added missing mutex_exit() at error path.

branches: 1.24.4;
Implement MI IPI interface with cross-call support.

branches: 1.23.2;
make pci_intr_string and eisa_intr_string take a buffer and a length
instead of relying in local static storage.

branches: 1.22.2;
Change a KASSERT to a KASSERTMSG.

branches: 1.21.2;
Add a machine splhist command to give (a incomplete) spl history.
(only the most recent are going to be accurate).

splraise(6) from 0 at 549214603
splraise(7) from 6 at 549214643 (+40)
splx(6) from 7 at 549214691 (+48)
splx(0) from 6 at 549214730 (+39)

Add two missing interrupt sources for P1025.

Add support for the Freescale TWR-P1025 evaluation board and the P1025/P1016
QorIQ processors. XXX tsec isn't working yet on the TWR-P1025.

If we paniced because a watchdog timed out, PSL_CE will be clear. So don't
assert PSL_CE is set if panicstr is not NULL.

Compute softintr mask correctly.

branches: 1.16.2; 1.16.8;
Modify *ASSERTMSG() so they are now used as variadic macros. The main goal
is to provide routines that do as KASSERT(9) says: append a message
to the panic format string when the assertion triggers, with optional
arguments.

Fix call sites to reflect the new definition.

Discussed on tech-kern@. See
http://mail-index.netbsd.org/tech-kern/2011/09/07/msg011427.html

Add missing $NetBSD$ and/or __KERNEL_RCSID.

Panic when an ipi is sent to unknown cpu.

Make powerpc work on BookE. At this time we only support DOZE (lightest
form of power-saving). By default, power-saving is disabled but can be
enabled in /etc/sysctl.conf by setting machdep.powersave=1

In e500_spl0, grab ci after disabling interrupts.
Consolidate a KASSERT.

Add IST_PULSE and intr_typename (converts IST_* to a name).

Take the fast softint support in e500_intr.c and make generic so that it can
be used to provide fast softint for other interrupt implementations.

Add an e500_idlespin to detect calls to idlespin when interrupts are blocked
or disabled.

Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

branches: 1.7.2;
Remove debugging printf. Add missing IMU2 interrupt string.

Add some grotty #ifdef'age to make this compile w/o DIAGNOSTIC.

Fix a bug in onchip_intr_name_lookup

Fix various nits related to P2020 support.

branches: 1.3.2;
Cleanup intr_info initialization. Make it per SVR.

branches: 1.2.2;
Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

branches: 1.1.2; 1.1.4;
file e500_intr.c was initially added on branch matt-nb5-pq3.

remove checks for failure after memory allocation calls that cannot fail:

kmem_alloc() with KM_SLEEP
kmem_zalloc() with KM_SLEEP
percpu_alloc()
pserialize_create()
psref_class_create()

all of these paths include an assertion that the allocation has not failed,
so callers should not assert that again.

Added MSI/MSI-X and interrupt_distribute(9) support for powerpc.

branches: 1.33.2;
__HAVE_PREEEMPTION -> __HAVE_PREEMPTION

Initialize timer DR.

ddb MP support

Allow to share IPI interrupt.

Initialize lock objects.

Preliminary support for P1023.

Revert previous commit.

Pass ci->ci_cpuid as irq of IST_IPI.
Avoid "panic: e500_intr_cpu_hatch: failed to establish ipi interrupt!" on cpu1.

Added missing mutex_exit() at error path.

branches: 1.24.4;
Implement MI IPI interface with cross-call support.

branches: 1.23.2;
make pci_intr_string and eisa_intr_string take a buffer and a length
instead of relying in local static storage.

branches: 1.22.2;
Change a KASSERT to a KASSERTMSG.

branches: 1.21.2;
Add a machine splhist command to give (a incomplete) spl history.
(only the most recent are going to be accurate).

splraise(6) from 0 at 549214603
splraise(7) from 6 at 549214643 (+40)
splx(6) from 7 at 549214691 (+48)
splx(0) from 6 at 549214730 (+39)

Add two missing interrupt sources for P1025.

Add support for the Freescale TWR-P1025 evaluation board and the P1025/P1016
QorIQ processors. XXX tsec isn't working yet on the TWR-P1025.

If we paniced because a watchdog timed out, PSL_CE will be clear. So don't
assert PSL_CE is set if panicstr is not NULL.

Compute softintr mask correctly.

branches: 1.16.2; 1.16.8;
Modify *ASSERTMSG() so they are now used as variadic macros. The main goal
is to provide routines that do as KASSERT(9) says: append a message
to the panic format string when the assertion triggers, with optional
arguments.

Fix call sites to reflect the new definition.

Discussed on tech-kern@. See
http://mail-index.netbsd.org/tech-kern/2011/09/07/msg011427.html

Add missing $NetBSD$ and/or __KERNEL_RCSID.

Panic when an ipi is sent to unknown cpu.

Make powerpc work on BookE. At this time we only support DOZE (lightest
form of power-saving). By default, power-saving is disabled but can be
enabled in /etc/sysctl.conf by setting machdep.powersave=1

In e500_spl0, grab ci after disabling interrupts.
Consolidate a KASSERT.

Add IST_PULSE and intr_typename (converts IST_* to a name).

Take the fast softint support in e500_intr.c and make generic so that it can
be used to provide fast softint for other interrupt implementations.

Add an e500_idlespin to detect calls to idlespin when interrupts are blocked
or disabled.