mips: Add missing barriers in cpu_switchto.

Details in comments.

PR kern/57240

XXX pullup-8
XXX pullup-9
XXX pullup-10

Add mipsNN_cp0_rdhwr_cpunum() which returns the current CPU number
read from the CPUNum hardware register on MIPS{32,64}R2.

Don't warn about MIPS1 MULTIPROCESSOR in a mips3 file.

Sprinle RCSID

branches: 1.112.2;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

Fix logic inversion in 1.107

.set mips3 for __mips_o32
now o32 kernels boot again on my O2

Don't include <machine/param.h> in .S files, get the needed values from assym.h
Define NBPG as UL to avoid integer over with NBXSEG on LP64 systems.
(.S files don't like numbers with UL appended to them).

Define COP0 register that use select value in <mips/cpuregs.h>
Use those new definitions

On mipsNN use trap instructions when inconsistent status register settings
are found.

Don't compile the mips64 stuff if we being compiled as mips32

Don't .set mips3 if we are >= mips3 already
Use dins if we have it rather than two shifts.

In cpu_trampoline, load the ksp from the idlelwp after we enable KX.

Rework cavium support in preparation for MULTIPROCESSOR support

branches: 1.102.12; 1.102.30;
Only jump through t9/ra (or k0) to help avoid hitting
the Loongson2 jump problem.

Add support for a loongson2_subr.S. This is needed since that chip needs
special handling to manually flush the ITLB on TLB updates.

More <machine/ include cleanup

Add mipsNN_cp0_watch{lo,hi}_{read,write}

Add separate support for MIPS32R2 and MIPS64R2.
Use EHB/SSNOP and jr.hb ra as appropriate (COP0_SYNC now uses them).
Add support for COP_0_HWRENA and COP_0_USERLOCAL (use by rdhwr $3,$29
instruction for TLS support).
Add mips3+ reserved instruction handler to emulate rdhwr is many fewer
instructions.

Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU

branches: 1.96.4; 1.96.6; 1.96.8;
Merge from matt-nb5-mips64
Merge mips-specific arch files.

Rename L_ADDR to L_PCB and amend some comments accordingly.

- Use uvm_lwp_setuarea() instead of directly setting address to lwp_t::l_addr.
- Replace most remaining uses of l_addr with uvm_lwp_getuarea() or lwp_getpcb().
- Amend assembly in ports where it accesses PCB via struct user.
- Rename L_ADDR to L_PCB in few places. Reduce sys/user.h inclusions.

branches: 1.93.20; 1.93.38;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.92.2; 1.92.10;
Fix typo.

merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.

branches: 1.90.4; 1.90.6; 1.90.12;
uvm.page_idle_zero now is a bool, not a 32bit value any more.

BTW, is it still worth to have uvm_pageidlezero()? Which port uses it?

branches: 1.89.2;
Merge newlock2 to head.

branches: 1.88.20;
merge ktrace-lwp.

Add mips3_cp0_pg_mask_write() to initialize pagemask register.

branches: 1.86.6; 1.86.14; 1.86.16;
Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.

branches: 1.85.2;
Merge the nathanw_sa branch.

branches: 1.84.4;
Sprinkle a little more COP0_SYNC (in an unused function...).

In the idle functions, set curproc to NULL and (#ifdef LOCKDEBUG) call
sched_unlock_idle before enabling interrupts. LOCKDEBUG kernels now
boot successfully.

Thanks to Chris Gilbert for helping fix this.

Include "opt_lockdebug.h" here to #ifdef LOCKDEBUG actually does something.

Fix tyop.

White space nits.

Use CPU_MIPS_USE_WAIT and CPU_MIPS_NO_WAIT in the CPU table, and use
the generic name "mips_wait_idle" for the old function that had both
rm52xx_idle and mipsNN_idle entry points.

Remove some unnecessary nops after some mfc0's.

branches: 1.77.4;
make this compile and work with MIPS3_5900.

Add support for MIPS32 and MIPS64 architectures:
- Remove all mmu-related code that may use 32 register on mips32-style
implementatios and move them to mipsX_subr.S - which is then included
from mips{3,32,64,5900}_subr.S with various control defines enabled.
- Remove local cache instruction flags
- Add badaddr64 (from Broadcom Corp).

add #ifdef DEBUG around VCED_count etc.

split VCED and VCEI.

simplify VCED processing.
just write back and invalidate secondary cache line and fetch data again.

branches: 1.72.2;
Merge the thorpej-mips-cache branch onto the trunk. This is an
overhaul of how caches are handled for NetBSD's MIPS ports.

branches: 1.71.2;
R5900 support.
COP0_SYNC
In R5900 mtc0, tlbr, tlbp, tlbwi, tlbwr must be followed by sync.p.
if defined MIPS3_5900, COP0_SYNC is defined as sync.p. else nothing.
IPL_ICU_MASK
mask interrupt directly ICU instead of SR.IM.
I've added this feature to support software interrupt for R5900.
and this option may be useful for platform which has cascaded ICU.

Fix bug in mips3_proc_trampoline: SR wasn't disabled on entry, allowing an
interrupt to sneak in after EXL had been set; the interrupt EPC was stale
as PC isn't saved if EXL is set, causing the eret to return to the wrong
place and leading to kernel-mode TLB misses on user addresses. The bug
was discovered by the japanese NetBSD/*mips folks and the same fix was
found independently by shinohara-san (shin@netbsd.org).

branches: 1.69.2;
Always indirect through the "locoresw" to get the cache ops, since
there are just far too many combinations to handle with magic
#ifdefs in any sane way. Also, add a HitFlushDCache op to the
"locoresw", and fill it in as appropriate (it's NULL on MIPS-I,
so watch out).

These changes ensure that my R4600 Indy (with 2-way cache) gets
the correct cache ops when the kernel is built with only MIPS3
support, resulting in a kernel that is significantly more stable.

add missing #include "opt_kgdb.h"

Add an idle loop routine for the QED RM52xx family. This uses the
RM52xx `wait' insn to power down the pipeline.

branches: 1.66.2;
Fix register name typo.

New syscall entry implementation based on the Alpha version
as hacked by mycroft.
- Use syscall_intern() to give a process a plain or fancy
syscall based on ktrace flags.
- Avoid copying from the trapframe into a local array as much
as possible.

Yields roughly 5% improvement on a 25MHz R3000 (DECstation 5000/200)
on a simple syscall benchmark.

There's still some work that can be done using __HAVE_MINIMAL_EMUL.

Make the astpending flag per-process.

Check for ASTs in Syscall and UserGenException, too; AST processing
must be done on *every* return to userland.

Hook mips3 cache error vector. No real handler, only set-up for a panic.
A real handler is hard.

For MIPS software masking option, when returning to user mode apply
the mask to all interrupts to catch changes in the mask state faster.
Does not affect platforms w/o this option enabled.

Use only one TLB entry to wire down process's USPACE since it's
now guranteed to be aligned on 8KB boundary in kernel virutal
address. Retain one more free TLB entry.

fix cp0 hazard.
R4000 requires 3 nops between tlbr and dmfc0.

In mips3_TBIS(va) do not invalidate the other half of the JTLB entry if
the page is wired down. Flushing both halves of a wired TLB entry resulted
in hangs when in programs called for and released kernel memory
soon after being invoked. In particular, we see this when single-stepping
a process using GDB.

It would be better if we could arrange to use both halves of the TLB
entry for the PCB, but for some reason we frequently end up with things
on an odd page boundary.

clean up and consistency for CP0 Count, Compare, Wired, and Config
access function names and prototypes.

nuke mips3_clearBEV(). There's really no point in coding a
special-purpose assembly routine for things like this.

provide mips3_ld() and mips3_sd(), functions which provide safe wrappers
for mips3 (and later) 'ld' and 'sd' instructions. These currently
only are properly implemented for the _MIPS_BSD_API_LP32 and
_MIPS_BSD_API_LP32_64CLEAN 'API's. They're pretty messy, but when you
need them, you really need them.

No longer save $at on syscall entry. v1 does appear to be used as if
you do not save it and pass it along in rval the system will start
to fail running user programs. This finishes the suggestion by cgd to
not save some registers on syscall entry.

Re-enable SR IE bit before calling syscall(). Matches Tohru's mips1 change.

Do not save t* registers in syscall stub as suggested by cgd. Saves
a whole 0.01us in lmbench lat_syscall null on our 250Mhz QED system.
$at is still saved just to be safe, although it looks like it does
not need to be. $v1 is used in syscall(), although I'm not sure why.

Introduce 'segbase' global variable to hold the pointer to current
process's segtab, retiring 'pcb_segtab' field from 'struct pcb'.
This would be another MULTIPROCESSOR unfriendly and the necessity
might be eliminated when the way to hold PTE is redesigned.

modify mips3 locore to elminate the abuse of XContext
so that we can run on systems that do not have XContext
(e.g. IDT 32364).

Remove old comment.

In outofworld, keep $sp for DDB case if it looks like a kernel address
so the stacktrace is ok.

Shuichiro URATA pointed out that the R4000 needs 3 nops. Other OSs make
it look at casual inspection like 1 nop is needed but play other tricks.
Still have reduced by 1 nop. Hopefully this covers the NEC 41[x]1. Could
not find info for those processors.

Remove 3 of the nops between tlbwr and eret in tlb miss handlers. They
were added early when adding the QED support. RM5231 seems to work fine
w/o the extra nops. Noticed by Chuck Cranor.

protect doubleword register from interrupt.

Make mips3_FlushICache() convert a0 into a KSEG0 + virtual index like
the _2way and mips3_FlushDCache(). This lets all mips3 cache ops accept
user virtual addresss w/o a tlb miss. Since this is now done in both
ICache flush routines, no need to do it in pmap.c. Fixed R4400
stability problems with setregs() cache flushing.

Fix mips3 outofworld to panic cleanly even if shutdown path misses K2.
Previously we jal to panic which never cleared the tlb fault, so if
on the course of shutdown (like a doshutdownhooks() callback) missed
K2, it would panic again. Fix by setting EPC to panic() and eret.

Add option to apply additional mask to the SR at run-time for MIPS3 platforms.
By default this is off, and only slightly changes the code to load SR when
a temp register is available. This can be used by the platform code to
handle slow to clear interrupts (our case) or to mask off any interrupt
any interrupt at run-time. This can be very useful for embedded platforms
that have less than desirable interrupt properties.

Include kgdb hooks in trap.c. Include bits of DDB code for kgdb also. Remove
some local prototypes that are in headers now.

Move masked status and instr into jal cpu_intr delay slot.

Improve outofworld: to include the vaddr. Removed unused mips3_Set64bit
and an #if 1.

Abandon {mips1,mips3}_TBRPL()s which have little gain. They were
expected to be better than MachTLBUpdate(). After all, TLBUpdate()
is rather harmful and should be replaced with TBIS().

Fix pasto.

branches: 1.36.2;
Add mips3_write_config().

put cache op #defines up at the top of the file, so all cache ops can
use them. Rename them to match the names in See Mips Run; they're not
as orthogonal as values or'd together might make you think... Finally,
actually use them for every bloody cache op.

Decrease MIPS3_TLB_WIRED_ENTRIES from 8 to 2,
and rename it to MIPS3_TLB_WIRED_UPAGES.
The value of wired register becomes variable on arc port,
and arc is the only mips3 port which uses the wired TLB entries 2..7.

typo in comment

Rename RM5200 cache ops to mips3_*_2way in anticipation of using them
for other CPUs with 2-way set associative L1 caches as well.

A few more white-space bogons.

branches: 1.30.2;
MachForceCacheUpdate and cacheflush_bug have never been used in NetBSD,
so remove references them, and do a little other cleanup.

Include opt_cputype.h.

mips5200_FlushCache(): flush L2 cache too.

Have mips_locoresw[] of 3 entry pointer array for different
implementation of locore routines between MIPS1 and MIPS3. It's
independent from mips_locore_jumpvec_t which is for cache/TLB
manipulating routines peculiar to processor designs. mips_locore_jumpvec_t
will be replaced with "processor closures" encapsulating implementation
parameters (cpuinfo) and pointers to conventaion routines (cpuops),
eventually.

Introduce mips3_TBRPL(); not used in this moment, to be useful to
discard MachTLBUpdate() calls, however, the necessity of TLB entry
modification in such a way is under question because implementation
glitches on ASID management was straightened, those calls can be
sanely removed after all.

delete unused function mips3_TLBReadVPS().
reorder insns to avoid mtc0/mfc0 hazard (for VR4100/R4700/RM52xx).
save/restore PageMask in mips3_TLBRead().

Effort to have consistent comments, fixing one error.

- Address PR#9907. u_pte[1] wired down is left not global sometimes.
The brokenness is revealed sporadorically by memory usage on runtime.
- Avoid Vr4100 incompatibilty by making sure to retain default pgMask
value for TLB invalidation routines.

- Implement mips3_TBIAP().
- Remove obsoluted routines in locore_mips3.S
- addiu -> addu, andi -> and, ori -> or.

Load delay slot is automagically adjusted at runtime since MIPS II
architecture.

Introduce cpu_intr() whose body is now provided by target ports in
their own ways. Ugly fixup #define in machine/intr.h have gone.
mips_hardware_intr global variable patch work has gone.

Make (sure) ASID management same as what NetBSD/alpha does for ASN.
ASID#0 is reserved for pmap0 shared between proc0 and kthreads,
and every TLB for KSEG2 has G (global) bit to have wildcard match
regardless of the process' ASID. MIPS1 would flush TLBs belong
to user spaces upon ASID generation bump. Change for MIPS3 is
to be done.

Updated RM5231 cache code from Jeff Smith and Ethan Solomita at Geocast.
Many thanks.

Disable the sN,sp,gp register restore code for now, as it seems to collide with
something else.

Make the MIPS1 and MIPS3 code more similar.
XXX Needs testing on MIPS1.

Take a whack at allowing sN, sp and gp to be set from DDB, too.

* news5000 support.
* mips3_VCE[DI] now support L2CacheLSize != 32.

reorder instructions in mips3_TLBFlush() to avoid coprocessor hazard
for R4600/R4700/VR4100.

Try to document the use of the XContext register in the TLBMiss and XTLBMiss
exception handlers.

Fix cut'n'pasto in comment.

branches: 1.10.2; 1.10.4; 1.10.6;
Changes for NetBSD/hpcmips.

Support VR4100.
Support 16KB page.
Support CPU without FPU.

Fix virtual alias problem(physio() case).

[new options]

options MIPS3_4100 /* VR4100 core */
options MIPS_16K_PAGE /* enable kernel support for 16k pages */
options SOFTFLOAT /* No FPU; avoid touching FPU registers */

Nuke register and remove trailling white space.

branches: 1.8.4;
ALIAS() is not needed, use XLEAF() or XNESTED() instead

Cannot do mcount() profiling in TLB exception-handler code.

Add VECTOR() and VECTOR_END() macros for declaring exception-vector
code. Fold in <xxx>End names used to copy exception code to vector
locations. Use in mips3 locore code.

Copy previous fix for TLB miss routine to XTLB miss routine to avoid
processor-dependent behavior in 32-bit ops on 64-bit operands.

Fix the TLBMiss handler to not use an undefined operation (32 bit operation
on 64 bit register that's not correctly signed extended. The R4x00 support
works again on DECstations. A similar change to the XTLBMiss handler probably
needs to be made, but I have not done that since I am unable to test any
changes to that.
Also re-order a couple of instructions to allow for delay with mfc0.

- Make cpu_switch() a normal call; formally it was splitted into halves.
- Fix an error in mips3_cpu_switch_resume(); ASID was not set correctly.
- Remove global variable 'curpcb' reference in mips1_proc_trampoline().
- Restore 'cpuregs.h'.

* Elimination of UADDR/KERNELSTACK

Affected files:
include/mips_param.h, include/pcb.h,
mips/locore_mips1.S, mips/locore_mips3.S,
mips/mips_machdep.c, mips/vm_machdep.c

Issue:

So far, NetBSD/mips has not successfully got rid of fixed-address
kernel stack. USPACE (two 4KB pages) of each process has two distinct
KSEG2 addresses, both refer to a single physical storage; one address
for fixed range [ UADDR .. KERNELSTACK ), and another for "normal" KSEG2
address which was allocated by kernel memory manager and unique to each
others of processes.

"Doubly mapped" USPACE complicates context switch. Both address ranges
have to be managed with a special care of "wired" TLB entries which
are never replaced until next context switch to ensure no TLB miss for
USPACE access. It's equally crumbersome that MIPS processor's cache
machinary gets be confused about USPACE contents because there are two
distinct KSEG2 addresses to manipulate one physical storage.

Solution:

Purge KERNELSTACK constant for kernel stack pointer and replace
it with process unique values. Kernel stack bottom is located at
'curproc->p_addr + USPACE'. Context switch is simplified as it unloads
half of TLB hardwiring burden. It just manages the unique KSEG2 address
of each USPACE to be wired. As the side effect, switch_exit() has no
MIPS processor ISA dependent code anymore. It switchs kernel stack to
proc0's USPACE which has KSEG0 address and no need of TLB entry.

* Extensive use of 'genassym.cf'

To hide target port dependent and/or processor register size dependent
constants from assembler routines, 'genassym.cf' now has an extentive
set of definitions for various constants and offset values of
structural objects. This change will contribute possible NetBSD/mips64
portability too.

* Separation and rename of locore_r2000/_r4000.S

Those files are now indepedent standalones from locore.S to ease
maintainance works, and renamed to match MIPS processor ISA version.

* Changes in kernel mode exception handlers

Kernel mode exception handlers hold exception contexts by pushing a
certain set of register values on stack for resuming kernel mode
processing. This context is now represented with 'struct trapframe',
which is smaller than full scale (user mode) exception context 'struct
frame'. Stack consumption of kernel mode exception services is now
similar to 4.4BSD/mips.

* Relocation of exception frame

User mode context 'struct frame' is moved to the very bottom of kernel
stack at 'curproc->p_addr + USPACE - sizeof(struct frame)' This change
saves a bit of instructions on every return to user processes as it
eliminates reference to global variable 'curpcb' each time.

* Refurblished DDB backtrace routine

It's a growing concern to maintain stacktrace() code correctly. It
could be simplified by enforcing special arrangements for some of
obscure locore routines which violate usual coding conventions.

New backtrace code searchs for certain instructions peculiar to any of
function tails. Specifically, "jr ra" for normal function returns, "jr
k0" for MIPS1 exception handlers and "eret" for MIPS3 handlers.

* Support for 64-bit safe user code
Affected Files:
${ARCH}/include/pubassym.cf lib/libc/arch/mips/gen/*setjmp*
include/setjmp.h mips/include/[lots] mips/mips/[lots]

Solution:

We define macros REG_L/REG_S and SZREG for loading and storing
registers and for the size of registers. The exact meaning
of these is controlled by a macro (currently _MIPS64) which
allows one to treat the registers as either 32-bit or 64-bit.
There are data types mips_reg_t and mips_fpreg_t which represent
the true register sizes, and avoid confusing register_t.

We needed a way to dynamically gen the structure sizes of things
like sigcontext for setjmp.h, so we defined a pubassym.cf for
libc routines like setjmp and longjmp.

NetBSD/mips allows ${ARCH}'s to be defined which preserve
all 64-bits of registers across user context switches. There
are still a few niceties to clean up for kernel mode context
switches.

* Support for QED 52xx processors
Affected Files:
mips/locore_mips3.S mips/pmap.c include/locore.h

Issue:
The QED 52xx family of processors are targeted at low cost
embedded systems, (i.e. CPUs ~$30) for systems like routers, printers,
etc. We have added preliminary support for some of the idiosyncrasies
of this processor, e.g. no L2 cache, etc. More work needs to be
done here because with a modest 2-way L1 cache, some of the rampant
flushing has significant performance implications. However,
it doesn't crash, which is a start.

Solution:
A routine for flushing the cache based on virtual addresses was added;
a routine which deals with the two-way set associativity of the
5230 L1 cache was added, accomodations to 5230's instruction hazards
were added.


* TLB Miss code for mips3/mips4 processors cleaned up significantly.
Affected Files:
mips/locore_mips3.S mips/vm_machdep.c include/locore.h mips_machdep.c
Issue:
The TLB Miss handler exceeded the allowed size, which wasn't
a problem because there was no handler for when the processor
was in 64-bit mode. The handler for invalid TLB exceptions
also appears to have much vestigial code, which made it
difficult to understand.

Solution:
Use the XCONTEXT register to store a pointer to the segment
map table, this coupled with removing some dead code allows
the handlers to fit.

branches: 1.1.2;
file locore_mips3.S was initially added on branch nisimura-pmax-wscons.

Add mipsNN_cp0_rdhwr_cpunum() which returns the current CPU number
read from the CPUNum hardware register on MIPS{32,64}R2.

Don't warn about MIPS1 MULTIPROCESSOR in a mips3 file.

Sprinle RCSID

branches: 1.112.2;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

Fix logic inversion in 1.107

.set mips3 for __mips_o32
now o32 kernels boot again on my O2

Don't include <machine/param.h> in .S files, get the needed values from assym.h
Define NBPG as UL to avoid integer over with NBXSEG on LP64 systems.
(.S files don't like numbers with UL appended to them).

Define COP0 register that use select value in <mips/cpuregs.h>
Use those new definitions

On mipsNN use trap instructions when inconsistent status register settings
are found.

Don't compile the mips64 stuff if we being compiled as mips32

Don't .set mips3 if we are >= mips3 already
Use dins if we have it rather than two shifts.

In cpu_trampoline, load the ksp from the idlelwp after we enable KX.

Rework cavium support in preparation for MULTIPROCESSOR support

branches: 1.102.12; 1.102.30;
Only jump through t9/ra (or k0) to help avoid hitting
the Loongson2 jump problem.

Add support for a loongson2_subr.S. This is needed since that chip needs
special handling to manually flush the ITLB on TLB updates.

More <machine/ include cleanup

Add mipsNN_cp0_watch{lo,hi}_{read,write}

Add separate support for MIPS32R2 and MIPS64R2.
Use EHB/SSNOP and jr.hb ra as appropriate (COP0_SYNC now uses them).
Add support for COP_0_HWRENA and COP_0_USERLOCAL (use by rdhwr $3,$29
instruction for TLS support).
Add mips3+ reserved instruction handler to emulate rdhwr is many fewer
instructions.

Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU

branches: 1.96.4; 1.96.6; 1.96.8;
Merge from matt-nb5-mips64
Merge mips-specific arch files.

Rename L_ADDR to L_PCB and amend some comments accordingly.

- Use uvm_lwp_setuarea() instead of directly setting address to lwp_t::l_addr.
- Replace most remaining uses of l_addr with uvm_lwp_getuarea() or lwp_getpcb().
- Amend assembly in ports where it accesses PCB via struct user.
- Rename L_ADDR to L_PCB in few places. Reduce sys/user.h inclusions.

branches: 1.93.20; 1.93.38;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.92.2; 1.92.10;
Fix typo.

merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.

branches: 1.90.4; 1.90.6; 1.90.12;
uvm.page_idle_zero now is a bool, not a 32bit value any more.

BTW, is it still worth to have uvm_pageidlezero()? Which port uses it?

branches: 1.89.2;
Merge newlock2 to head.

branches: 1.88.20;
merge ktrace-lwp.

Add mips3_cp0_pg_mask_write() to initialize pagemask register.

branches: 1.86.6; 1.86.14; 1.86.16;
Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.

branches: 1.85.2;
Merge the nathanw_sa branch.

branches: 1.84.4;
Sprinkle a little more COP0_SYNC (in an unused function...).

In the idle functions, set curproc to NULL and (#ifdef LOCKDEBUG) call
sched_unlock_idle before enabling interrupts. LOCKDEBUG kernels now
boot successfully.

Thanks to Chris Gilbert for helping fix this.

Include "opt_lockdebug.h" here to #ifdef LOCKDEBUG actually does something.

Fix tyop.

White space nits.

Use CPU_MIPS_USE_WAIT and CPU_MIPS_NO_WAIT in the CPU table, and use
the generic name "mips_wait_idle" for the old function that had both
rm52xx_idle and mipsNN_idle entry points.

Remove some unnecessary nops after some mfc0's.

branches: 1.77.4;
make this compile and work with MIPS3_5900.

Add support for MIPS32 and MIPS64 architectures:
- Remove all mmu-related code that may use 32 register on mips32-style
implementatios and move them to mipsX_subr.S - which is then included
from mips{3,32,64,5900}_subr.S with various control defines enabled.
- Remove local cache instruction flags
- Add badaddr64 (from Broadcom Corp).

add #ifdef DEBUG around VCED_count etc.

split VCED and VCEI.

simplify VCED processing.
just write back and invalidate secondary cache line and fetch data again.

branches: 1.72.2;
Merge the thorpej-mips-cache branch onto the trunk. This is an
overhaul of how caches are handled for NetBSD's MIPS ports.

branches: 1.71.2;
R5900 support.
COP0_SYNC
In R5900 mtc0, tlbr, tlbp, tlbwi, tlbwr must be followed by sync.p.
if defined MIPS3_5900, COP0_SYNC is defined as sync.p. else nothing.
IPL_ICU_MASK
mask interrupt directly ICU instead of SR.IM.
I've added this feature to support software interrupt for R5900.
and this option may be useful for platform which has cascaded ICU.

Fix bug in mips3_proc_trampoline: SR wasn't disabled on entry, allowing an
interrupt to sneak in after EXL had been set; the interrupt EPC was stale
as PC isn't saved if EXL is set, causing the eret to return to the wrong
place and leading to kernel-mode TLB misses on user addresses. The bug
was discovered by the japanese NetBSD/*mips folks and the same fix was
found independently by shinohara-san (shin@netbsd.org).

branches: 1.69.2;
Always indirect through the "locoresw" to get the cache ops, since
there are just far too many combinations to handle with magic
#ifdefs in any sane way. Also, add a HitFlushDCache op to the
"locoresw", and fill it in as appropriate (it's NULL on MIPS-I,
so watch out).

These changes ensure that my R4600 Indy (with 2-way cache) gets
the correct cache ops when the kernel is built with only MIPS3
support, resulting in a kernel that is significantly more stable.

add missing #include "opt_kgdb.h"

Add an idle loop routine for the QED RM52xx family. This uses the
RM52xx `wait' insn to power down the pipeline.

branches: 1.66.2;
Fix register name typo.

New syscall entry implementation based on the Alpha version
as hacked by mycroft.
- Use syscall_intern() to give a process a plain or fancy
syscall based on ktrace flags.
- Avoid copying from the trapframe into a local array as much
as possible.

Yields roughly 5% improvement on a 25MHz R3000 (DECstation 5000/200)
on a simple syscall benchmark.

There's still some work that can be done using __HAVE_MINIMAL_EMUL.

Make the astpending flag per-process.

Check for ASTs in Syscall and UserGenException, too; AST processing
must be done on *every* return to userland.

Hook mips3 cache error vector. No real handler, only set-up for a panic.
A real handler is hard.

For MIPS software masking option, when returning to user mode apply
the mask to all interrupts to catch changes in the mask state faster.
Does not affect platforms w/o this option enabled.

Use only one TLB entry to wire down process's USPACE since it's
now guranteed to be aligned on 8KB boundary in kernel virutal
address. Retain one more free TLB entry.

fix cp0 hazard.
R4000 requires 3 nops between tlbr and dmfc0.

In mips3_TBIS(va) do not invalidate the other half of the JTLB entry if
the page is wired down. Flushing both halves of a wired TLB entry resulted
in hangs when in programs called for and released kernel memory
soon after being invoked. In particular, we see this when single-stepping
a process using GDB.

It would be better if we could arrange to use both halves of the TLB
entry for the PCB, but for some reason we frequently end up with things
on an odd page boundary.

clean up and consistency for CP0 Count, Compare, Wired, and Config
access function names and prototypes.

nuke mips3_clearBEV(). There's really no point in coding a
special-purpose assembly routine for things like this.

provide mips3_ld() and mips3_sd(), functions which provide safe wrappers
for mips3 (and later) 'ld' and 'sd' instructions. These currently
only are properly implemented for the _MIPS_BSD_API_LP32 and
_MIPS_BSD_API_LP32_64CLEAN 'API's. They're pretty messy, but when you
need them, you really need them.

No longer save $at on syscall entry. v1 does appear to be used as if
you do not save it and pass it along in rval the system will start
to fail running user programs. This finishes the suggestion by cgd to
not save some registers on syscall entry.

Re-enable SR IE bit before calling syscall(). Matches Tohru's mips1 change.

Do not save t* registers in syscall stub as suggested by cgd. Saves
a whole 0.01us in lmbench lat_syscall null on our 250Mhz QED system.
$at is still saved just to be safe, although it looks like it does
not need to be. $v1 is used in syscall(), although I'm not sure why.

Introduce 'segbase' global variable to hold the pointer to current
process's segtab, retiring 'pcb_segtab' field from 'struct pcb'.
This would be another MULTIPROCESSOR unfriendly and the necessity
might be eliminated when the way to hold PTE is redesigned.

modify mips3 locore to elminate the abuse of XContext
so that we can run on systems that do not have XContext
(e.g. IDT 32364).

Remove old comment.

In outofworld, keep $sp for DDB case if it looks like a kernel address
so the stacktrace is ok.

Shuichiro URATA pointed out that the R4000 needs 3 nops. Other OSs make
it look at casual inspection like 1 nop is needed but play other tricks.
Still have reduced by 1 nop. Hopefully this covers the NEC 41[x]1. Could
not find info for those processors.

Remove 3 of the nops between tlbwr and eret in tlb miss handlers. They
were added early when adding the QED support. RM5231 seems to work fine
w/o the extra nops. Noticed by Chuck Cranor.

protect doubleword register from interrupt.

Make mips3_FlushICache() convert a0 into a KSEG0 + virtual index like
the _2way and mips3_FlushDCache(). This lets all mips3 cache ops accept
user virtual addresss w/o a tlb miss. Since this is now done in both
ICache flush routines, no need to do it in pmap.c. Fixed R4400
stability problems with setregs() cache flushing.

Fix mips3 outofworld to panic cleanly even if shutdown path misses K2.
Previously we jal to panic which never cleared the tlb fault, so if
on the course of shutdown (like a doshutdownhooks() callback) missed
K2, it would panic again. Fix by setting EPC to panic() and eret.

Add option to apply additional mask to the SR at run-time for MIPS3 platforms.
By default this is off, and only slightly changes the code to load SR when
a temp register is available. This can be used by the platform code to
handle slow to clear interrupts (our case) or to mask off any interrupt
any interrupt at run-time. This can be very useful for embedded platforms
that have less than desirable interrupt properties.

Include kgdb hooks in trap.c. Include bits of DDB code for kgdb also. Remove
some local prototypes that are in headers now.

Move masked status and instr into jal cpu_intr delay slot.

Improve outofworld: to include the vaddr. Removed unused mips3_Set64bit
and an #if 1.

Abandon {mips1,mips3}_TBRPL()s which have little gain. They were
expected to be better than MachTLBUpdate(). After all, TLBUpdate()
is rather harmful and should be replaced with TBIS().

Fix pasto.

branches: 1.36.2;
Add mips3_write_config().

put cache op #defines up at the top of the file, so all cache ops can
use them. Rename them to match the names in See Mips Run; they're not
as orthogonal as values or'd together might make you think... Finally,
actually use them for every bloody cache op.

Decrease MIPS3_TLB_WIRED_ENTRIES from 8 to 2,
and rename it to MIPS3_TLB_WIRED_UPAGES.
The value of wired register becomes variable on arc port,
and arc is the only mips3 port which uses the wired TLB entries 2..7.

typo in comment

Rename RM5200 cache ops to mips3_*_2way in anticipation of using them
for other CPUs with 2-way set associative L1 caches as well.

A few more white-space bogons.

branches: 1.30.2;
MachForceCacheUpdate and cacheflush_bug have never been used in NetBSD,
so remove references them, and do a little other cleanup.

Include opt_cputype.h.

mips5200_FlushCache(): flush L2 cache too.

Have mips_locoresw[] of 3 entry pointer array for different
implementation of locore routines between MIPS1 and MIPS3. It's
independent from mips_locore_jumpvec_t which is for cache/TLB
manipulating routines peculiar to processor designs. mips_locore_jumpvec_t
will be replaced with "processor closures" encapsulating implementation
parameters (cpuinfo) and pointers to conventaion routines (cpuops),
eventually.

Introduce mips3_TBRPL(); not used in this moment, to be useful to
discard MachTLBUpdate() calls, however, the necessity of TLB entry
modification in such a way is under question because implementation
glitches on ASID management was straightened, those calls can be
sanely removed after all.

delete unused function mips3_TLBReadVPS().
reorder insns to avoid mtc0/mfc0 hazard (for VR4100/R4700/RM52xx).
save/restore PageMask in mips3_TLBRead().

Effort to have consistent comments, fixing one error.

- Address PR#9907. u_pte[1] wired down is left not global sometimes.
The brokenness is revealed sporadorically by memory usage on runtime.
- Avoid Vr4100 incompatibilty by making sure to retain default pgMask
value for TLB invalidation routines.

- Implement mips3_TBIAP().
- Remove obsoluted routines in locore_mips3.S
- addiu -> addu, andi -> and, ori -> or.

Load delay slot is automagically adjusted at runtime since MIPS II
architecture.

Introduce cpu_intr() whose body is now provided by target ports in
their own ways. Ugly fixup #define in machine/intr.h have gone.
mips_hardware_intr global variable patch work has gone.

Make (sure) ASID management same as what NetBSD/alpha does for ASN.
ASID#0 is reserved for pmap0 shared between proc0 and kthreads,
and every TLB for KSEG2 has G (global) bit to have wildcard match
regardless of the process' ASID. MIPS1 would flush TLBs belong
to user spaces upon ASID generation bump. Change for MIPS3 is
to be done.

Updated RM5231 cache code from Jeff Smith and Ethan Solomita at Geocast.
Many thanks.

Disable the sN,sp,gp register restore code for now, as it seems to collide with
something else.

Make the MIPS1 and MIPS3 code more similar.
XXX Needs testing on MIPS1.

Take a whack at allowing sN, sp and gp to be set from DDB, too.

* news5000 support.
* mips3_VCE[DI] now support L2CacheLSize != 32.

reorder instructions in mips3_TLBFlush() to avoid coprocessor hazard
for R4600/R4700/VR4100.

Try to document the use of the XContext register in the TLBMiss and XTLBMiss
exception handlers.

Fix cut'n'pasto in comment.

branches: 1.10.2; 1.10.4; 1.10.6;
Changes for NetBSD/hpcmips.

Support VR4100.
Support 16KB page.
Support CPU without FPU.

Fix virtual alias problem(physio() case).

[new options]

options MIPS3_4100 /* VR4100 core */
options MIPS_16K_PAGE /* enable kernel support for 16k pages */
options SOFTFLOAT /* No FPU; avoid touching FPU registers */

Nuke register and remove trailling white space.

branches: 1.8.4;
ALIAS() is not needed, use XLEAF() or XNESTED() instead

Cannot do mcount() profiling in TLB exception-handler code.

Add VECTOR() and VECTOR_END() macros for declaring exception-vector
code. Fold in <xxx>End names used to copy exception code to vector
locations. Use in mips3 locore code.

Copy previous fix for TLB miss routine to XTLB miss routine to avoid
processor-dependent behavior in 32-bit ops on 64-bit operands.

Fix the TLBMiss handler to not use an undefined operation (32 bit operation
on 64 bit register that's not correctly signed extended. The R4x00 support
works again on DECstations. A similar change to the XTLBMiss handler probably
needs to be made, but I have not done that since I am unable to test any
changes to that.
Also re-order a couple of instructions to allow for delay with mfc0.

- Make cpu_switch() a normal call; formally it was splitted into halves.
- Fix an error in mips3_cpu_switch_resume(); ASID was not set correctly.
- Remove global variable 'curpcb' reference in mips1_proc_trampoline().
- Restore 'cpuregs.h'.

* Elimination of UADDR/KERNELSTACK

Affected files:
include/mips_param.h, include/pcb.h,
mips/locore_mips1.S, mips/locore_mips3.S,
mips/mips_machdep.c, mips/vm_machdep.c

Issue:

So far, NetBSD/mips has not successfully got rid of fixed-address
kernel stack. USPACE (two 4KB pages) of each process has two distinct
KSEG2 addresses, both refer to a single physical storage; one address
for fixed range [ UADDR .. KERNELSTACK ), and another for "normal" KSEG2
address which was allocated by kernel memory manager and unique to each
others of processes.

"Doubly mapped" USPACE complicates context switch. Both address ranges
have to be managed with a special care of "wired" TLB entries which
are never replaced until next context switch to ensure no TLB miss for
USPACE access. It's equally crumbersome that MIPS processor's cache
machinary gets be confused about USPACE contents because there are two
distinct KSEG2 addresses to manipulate one physical storage.

Solution:

Purge KERNELSTACK constant for kernel stack pointer and replace
it with process unique values. Kernel stack bottom is located at
'curproc->p_addr + USPACE'. Context switch is simplified as it unloads
half of TLB hardwiring burden. It just manages the unique KSEG2 address
of each USPACE to be wired. As the side effect, switch_exit() has no
MIPS processor ISA dependent code anymore. It switchs kernel stack to
proc0's USPACE which has KSEG0 address and no need of TLB entry.

* Extensive use of 'genassym.cf'

To hide target port dependent and/or processor register size dependent
constants from assembler routines, 'genassym.cf' now has an extentive
set of definitions for various constants and offset values of
structural objects. This change will contribute possible NetBSD/mips64
portability too.

* Separation and rename of locore_r2000/_r4000.S

Those files are now indepedent standalones from locore.S to ease
maintainance works, and renamed to match MIPS processor ISA version.

* Changes in kernel mode exception handlers

Kernel mode exception handlers hold exception contexts by pushing a
certain set of register values on stack for resuming kernel mode
processing. This context is now represented with 'struct trapframe',
which is smaller than full scale (user mode) exception context 'struct
frame'. Stack consumption of kernel mode exception services is now
similar to 4.4BSD/mips.

* Relocation of exception frame

User mode context 'struct frame' is moved to the very bottom of kernel
stack at 'curproc->p_addr + USPACE - sizeof(struct frame)' This change
saves a bit of instructions on every return to user processes as it
eliminates reference to global variable 'curpcb' each time.

* Refurblished DDB backtrace routine

It's a growing concern to maintain stacktrace() code correctly. It
could be simplified by enforcing special arrangements for some of
obscure locore routines which violate usual coding conventions.

New backtrace code searchs for certain instructions peculiar to any of
function tails. Specifically, "jr ra" for normal function returns, "jr
k0" for MIPS1 exception handlers and "eret" for MIPS3 handlers.

* Support for 64-bit safe user code
Affected Files:
${ARCH}/include/pubassym.cf lib/libc/arch/mips/gen/*setjmp*
include/setjmp.h mips/include/[lots] mips/mips/[lots]

Solution:

We define macros REG_L/REG_S and SZREG for loading and storing
registers and for the size of registers. The exact meaning
of these is controlled by a macro (currently _MIPS64) which
allows one to treat the registers as either 32-bit or 64-bit.
There are data types mips_reg_t and mips_fpreg_t which represent
the true register sizes, and avoid confusing register_t.

We needed a way to dynamically gen the structure sizes of things
like sigcontext for setjmp.h, so we defined a pubassym.cf for
libc routines like setjmp and longjmp.

NetBSD/mips allows ${ARCH}'s to be defined which preserve
all 64-bits of registers across user context switches. There
are still a few niceties to clean up for kernel mode context
switches.

* Support for QED 52xx processors
Affected Files:
mips/locore_mips3.S mips/pmap.c include/locore.h

Issue:
The QED 52xx family of processors are targeted at low cost
embedded systems, (i.e. CPUs ~$30) for systems like routers, printers,
etc. We have added preliminary support for some of the idiosyncrasies
of this processor, e.g. no L2 cache, etc. More work needs to be
done here because with a modest 2-way L1 cache, some of the rampant
flushing has significant performance implications. However,
it doesn't crash, which is a start.

Solution:
A routine for flushing the cache based on virtual addresses was added;
a routine which deals with the two-way set associativity of the
5230 L1 cache was added, accomodations to 5230's instruction hazards
were added.


* TLB Miss code for mips3/mips4 processors cleaned up significantly.
Affected Files:
mips/locore_mips3.S mips/vm_machdep.c include/locore.h mips_machdep.c
Issue:
The TLB Miss handler exceeded the allowed size, which wasn't
a problem because there was no handler for when the processor
was in 64-bit mode. The handler for invalid TLB exceptions
also appears to have much vestigial code, which made it
difficult to understand.

Solution:
Use the XCONTEXT register to store a pointer to the segment
map table, this coupled with removing some dead code allows
the handlers to fit.

branches: 1.1.2;
file locore_mips3.S was initially added on branch nisimura-pmax-wscons.

Don't warn about MIPS1 MULTIPROCESSOR in a mips3 file.

Sprinle RCSID

branches: 1.112.2;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

Fix logic inversion in 1.107

.set mips3 for __mips_o32
now o32 kernels boot again on my O2

Don't include <machine/param.h> in .S files, get the needed values from assym.h
Define NBPG as UL to avoid integer over with NBXSEG on LP64 systems.
(.S files don't like numbers with UL appended to them).

Define COP0 register that use select value in <mips/cpuregs.h>
Use those new definitions

On mipsNN use trap instructions when inconsistent status register settings
are found.

Don't compile the mips64 stuff if we being compiled as mips32

Don't .set mips3 if we are >= mips3 already
Use dins if we have it rather than two shifts.

In cpu_trampoline, load the ksp from the idlelwp after we enable KX.

Rework cavium support in preparation for MULTIPROCESSOR support

branches: 1.102.12; 1.102.30;
Only jump through t9/ra (or k0) to help avoid hitting
the Loongson2 jump problem.

Add support for a loongson2_subr.S. This is needed since that chip needs
special handling to manually flush the ITLB on TLB updates.

More <machine/ include cleanup

Add mipsNN_cp0_watch{lo,hi}_{read,write}

Add separate support for MIPS32R2 and MIPS64R2.
Use EHB/SSNOP and jr.hb ra as appropriate (COP0_SYNC now uses them).
Add support for COP_0_HWRENA and COP_0_USERLOCAL (use by rdhwr $3,$29
instruction for TLS support).
Add mips3+ reserved instruction handler to emulate rdhwr is many fewer
instructions.

Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU

branches: 1.96.4; 1.96.6; 1.96.8;
Merge from matt-nb5-mips64
Merge mips-specific arch files.

Rename L_ADDR to L_PCB and amend some comments accordingly.

- Use uvm_lwp_setuarea() instead of directly setting address to lwp_t::l_addr.
- Replace most remaining uses of l_addr with uvm_lwp_getuarea() or lwp_getpcb().
- Amend assembly in ports where it accesses PCB via struct user.
- Rename L_ADDR to L_PCB in few places. Reduce sys/user.h inclusions.

branches: 1.93.20; 1.93.38;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.92.2; 1.92.10;
Fix typo.

merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.

branches: 1.90.4; 1.90.6; 1.90.12;
uvm.page_idle_zero now is a bool, not a 32bit value any more.

BTW, is it still worth to have uvm_pageidlezero()? Which port uses it?

branches: 1.89.2;
Merge newlock2 to head.

branches: 1.88.20;
merge ktrace-lwp.

Add mips3_cp0_pg_mask_write() to initialize pagemask register.

branches: 1.86.6; 1.86.14; 1.86.16;
Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.

branches: 1.85.2;
Merge the nathanw_sa branch.

branches: 1.84.4;
Sprinkle a little more COP0_SYNC (in an unused function...).

In the idle functions, set curproc to NULL and (#ifdef LOCKDEBUG) call
sched_unlock_idle before enabling interrupts. LOCKDEBUG kernels now
boot successfully.

Thanks to Chris Gilbert for helping fix this.

Include "opt_lockdebug.h" here to #ifdef LOCKDEBUG actually does something.

Fix tyop.

White space nits.

Use CPU_MIPS_USE_WAIT and CPU_MIPS_NO_WAIT in the CPU table, and use
the generic name "mips_wait_idle" for the old function that had both
rm52xx_idle and mipsNN_idle entry points.

Remove some unnecessary nops after some mfc0's.

branches: 1.77.4;
make this compile and work with MIPS3_5900.

Add support for MIPS32 and MIPS64 architectures:
- Remove all mmu-related code that may use 32 register on mips32-style
implementatios and move them to mipsX_subr.S - which is then included
from mips{3,32,64,5900}_subr.S with various control defines enabled.
- Remove local cache instruction flags
- Add badaddr64 (from Broadcom Corp).

add #ifdef DEBUG around VCED_count etc.

split VCED and VCEI.

simplify VCED processing.
just write back and invalidate secondary cache line and fetch data again.

branches: 1.72.2;
Merge the thorpej-mips-cache branch onto the trunk. This is an
overhaul of how caches are handled for NetBSD's MIPS ports.

branches: 1.71.2;
R5900 support.
COP0_SYNC
In R5900 mtc0, tlbr, tlbp, tlbwi, tlbwr must be followed by sync.p.
if defined MIPS3_5900, COP0_SYNC is defined as sync.p. else nothing.
IPL_ICU_MASK
mask interrupt directly ICU instead of SR.IM.
I've added this feature to support software interrupt for R5900.
and this option may be useful for platform which has cascaded ICU.

Fix bug in mips3_proc_trampoline: SR wasn't disabled on entry, allowing an
interrupt to sneak in after EXL had been set; the interrupt EPC was stale
as PC isn't saved if EXL is set, causing the eret to return to the wrong
place and leading to kernel-mode TLB misses on user addresses. The bug
was discovered by the japanese NetBSD/*mips folks and the same fix was
found independently by shinohara-san (shin@netbsd.org).

branches: 1.69.2;
Always indirect through the "locoresw" to get the cache ops, since
there are just far too many combinations to handle with magic
#ifdefs in any sane way. Also, add a HitFlushDCache op to the
"locoresw", and fill it in as appropriate (it's NULL on MIPS-I,
so watch out).

These changes ensure that my R4600 Indy (with 2-way cache) gets
the correct cache ops when the kernel is built with only MIPS3
support, resulting in a kernel that is significantly more stable.

add missing #include "opt_kgdb.h"

Add an idle loop routine for the QED RM52xx family. This uses the
RM52xx `wait' insn to power down the pipeline.

branches: 1.66.2;
Fix register name typo.

New syscall entry implementation based on the Alpha version
as hacked by mycroft.
- Use syscall_intern() to give a process a plain or fancy
syscall based on ktrace flags.
- Avoid copying from the trapframe into a local array as much
as possible.

Yields roughly 5% improvement on a 25MHz R3000 (DECstation 5000/200)
on a simple syscall benchmark.

There's still some work that can be done using __HAVE_MINIMAL_EMUL.

Make the astpending flag per-process.

Check for ASTs in Syscall and UserGenException, too; AST processing
must be done on *every* return to userland.

Hook mips3 cache error vector. No real handler, only set-up for a panic.
A real handler is hard.

For MIPS software masking option, when returning to user mode apply
the mask to all interrupts to catch changes in the mask state faster.
Does not affect platforms w/o this option enabled.

Use only one TLB entry to wire down process's USPACE since it's
now guranteed to be aligned on 8KB boundary in kernel virutal
address. Retain one more free TLB entry.

fix cp0 hazard.
R4000 requires 3 nops between tlbr and dmfc0.

In mips3_TBIS(va) do not invalidate the other half of the JTLB entry if
the page is wired down. Flushing both halves of a wired TLB entry resulted
in hangs when in programs called for and released kernel memory
soon after being invoked. In particular, we see this when single-stepping
a process using GDB.

It would be better if we could arrange to use both halves of the TLB
entry for the PCB, but for some reason we frequently end up with things
on an odd page boundary.

clean up and consistency for CP0 Count, Compare, Wired, and Config
access function names and prototypes.

nuke mips3_clearBEV(). There's really no point in coding a
special-purpose assembly routine for things like this.

provide mips3_ld() and mips3_sd(), functions which provide safe wrappers
for mips3 (and later) 'ld' and 'sd' instructions. These currently
only are properly implemented for the _MIPS_BSD_API_LP32 and
_MIPS_BSD_API_LP32_64CLEAN 'API's. They're pretty messy, but when you
need them, you really need them.

No longer save $at on syscall entry. v1 does appear to be used as if
you do not save it and pass it along in rval the system will start
to fail running user programs. This finishes the suggestion by cgd to
not save some registers on syscall entry.

Re-enable SR IE bit before calling syscall(). Matches Tohru's mips1 change.

Do not save t* registers in syscall stub as suggested by cgd. Saves
a whole 0.01us in lmbench lat_syscall null on our 250Mhz QED system.
$at is still saved just to be safe, although it looks like it does
not need to be. $v1 is used in syscall(), although I'm not sure why.

Introduce 'segbase' global variable to hold the pointer to current
process's segtab, retiring 'pcb_segtab' field from 'struct pcb'.
This would be another MULTIPROCESSOR unfriendly and the necessity
might be eliminated when the way to hold PTE is redesigned.

modify mips3 locore to elminate the abuse of XContext
so that we can run on systems that do not have XContext
(e.g. IDT 32364).

Remove old comment.

In outofworld, keep $sp for DDB case if it looks like a kernel address
so the stacktrace is ok.

Shuichiro URATA pointed out that the R4000 needs 3 nops. Other OSs make
it look at casual inspection like 1 nop is needed but play other tricks.
Still have reduced by 1 nop. Hopefully this covers the NEC 41[x]1. Could
not find info for those processors.

Remove 3 of the nops between tlbwr and eret in tlb miss handlers. They
were added early when adding the QED support. RM5231 seems to work fine
w/o the extra nops. Noticed by Chuck Cranor.

protect doubleword register from interrupt.

Make mips3_FlushICache() convert a0 into a KSEG0 + virtual index like
the _2way and mips3_FlushDCache(). This lets all mips3 cache ops accept
user virtual addresss w/o a tlb miss. Since this is now done in both
ICache flush routines, no need to do it in pmap.c. Fixed R4400
stability problems with setregs() cache flushing.

Fix mips3 outofworld to panic cleanly even if shutdown path misses K2.
Previously we jal to panic which never cleared the tlb fault, so if
on the course of shutdown (like a doshutdownhooks() callback) missed
K2, it would panic again. Fix by setting EPC to panic() and eret.

Add option to apply additional mask to the SR at run-time for MIPS3 platforms.
By default this is off, and only slightly changes the code to load SR when
a temp register is available. This can be used by the platform code to
handle slow to clear interrupts (our case) or to mask off any interrupt
any interrupt at run-time. This can be very useful for embedded platforms
that have less than desirable interrupt properties.

Include kgdb hooks in trap.c. Include bits of DDB code for kgdb also. Remove
some local prototypes that are in headers now.

Move masked status and instr into jal cpu_intr delay slot.

Improve outofworld: to include the vaddr. Removed unused mips3_Set64bit
and an #if 1.

Abandon {mips1,mips3}_TBRPL()s which have little gain. They were
expected to be better than MachTLBUpdate(). After all, TLBUpdate()
is rather harmful and should be replaced with TBIS().

Fix pasto.

branches: 1.36.2;
Add mips3_write_config().

put cache op #defines up at the top of the file, so all cache ops can
use them. Rename them to match the names in See Mips Run; they're not
as orthogonal as values or'd together might make you think... Finally,
actually use them for every bloody cache op.

Decrease MIPS3_TLB_WIRED_ENTRIES from 8 to 2,
and rename it to MIPS3_TLB_WIRED_UPAGES.
The value of wired register becomes variable on arc port,
and arc is the only mips3 port which uses the wired TLB entries 2..7.

typo in comment

Rename RM5200 cache ops to mips3_*_2way in anticipation of using them
for other CPUs with 2-way set associative L1 caches as well.

A few more white-space bogons.

branches: 1.30.2;
MachForceCacheUpdate and cacheflush_bug have never been used in NetBSD,
so remove references them, and do a little other cleanup.

Include opt_cputype.h.

mips5200_FlushCache(): flush L2 cache too.

Have mips_locoresw[] of 3 entry pointer array for different
implementation of locore routines between MIPS1 and MIPS3. It's
independent from mips_locore_jumpvec_t which is for cache/TLB
manipulating routines peculiar to processor designs. mips_locore_jumpvec_t
will be replaced with "processor closures" encapsulating implementation
parameters (cpuinfo) and pointers to conventaion routines (cpuops),
eventually.

Introduce mips3_TBRPL(); not used in this moment, to be useful to
discard MachTLBUpdate() calls, however, the necessity of TLB entry
modification in such a way is under question because implementation
glitches on ASID management was straightened, those calls can be
sanely removed after all.

delete unused function mips3_TLBReadVPS().
reorder insns to avoid mtc0/mfc0 hazard (for VR4100/R4700/RM52xx).
save/restore PageMask in mips3_TLBRead().

Effort to have consistent comments, fixing one error.

- Address PR#9907. u_pte[1] wired down is left not global sometimes.
The brokenness is revealed sporadorically by memory usage on runtime.
- Avoid Vr4100 incompatibilty by making sure to retain default pgMask
value for TLB invalidation routines.

- Implement mips3_TBIAP().
- Remove obsoluted routines in locore_mips3.S
- addiu -> addu, andi -> and, ori -> or.

Load delay slot is automagically adjusted at runtime since MIPS II
architecture.

Introduce cpu_intr() whose body is now provided by target ports in
their own ways. Ugly fixup #define in machine/intr.h have gone.
mips_hardware_intr global variable patch work has gone.

Make (sure) ASID management same as what NetBSD/alpha does for ASN.
ASID#0 is reserved for pmap0 shared between proc0 and kthreads,
and every TLB for KSEG2 has G (global) bit to have wildcard match
regardless of the process' ASID. MIPS1 would flush TLBs belong
to user spaces upon ASID generation bump. Change for MIPS3 is
to be done.

Updated RM5231 cache code from Jeff Smith and Ethan Solomita at Geocast.
Many thanks.

Disable the sN,sp,gp register restore code for now, as it seems to collide with
something else.

Make the MIPS1 and MIPS3 code more similar.
XXX Needs testing on MIPS1.

Take a whack at allowing sN, sp and gp to be set from DDB, too.

* news5000 support.
* mips3_VCE[DI] now support L2CacheLSize != 32.

reorder instructions in mips3_TLBFlush() to avoid coprocessor hazard
for R4600/R4700/VR4100.

Try to document the use of the XContext register in the TLBMiss and XTLBMiss
exception handlers.

Fix cut'n'pasto in comment.

branches: 1.10.2; 1.10.4; 1.10.6;
Changes for NetBSD/hpcmips.

Support VR4100.
Support 16KB page.
Support CPU without FPU.

Fix virtual alias problem(physio() case).

[new options]

options MIPS3_4100 /* VR4100 core */
options MIPS_16K_PAGE /* enable kernel support for 16k pages */
options SOFTFLOAT /* No FPU; avoid touching FPU registers */

Nuke register and remove trailling white space.

branches: 1.8.4;
ALIAS() is not needed, use XLEAF() or XNESTED() instead

Cannot do mcount() profiling in TLB exception-handler code.

Add VECTOR() and VECTOR_END() macros for declaring exception-vector
code. Fold in <xxx>End names used to copy exception code to vector
locations. Use in mips3 locore code.

Copy previous fix for TLB miss routine to XTLB miss routine to avoid
processor-dependent behavior in 32-bit ops on 64-bit operands.

Fix the TLBMiss handler to not use an undefined operation (32 bit operation
on 64 bit register that's not correctly signed extended. The R4x00 support
works again on DECstations. A similar change to the XTLBMiss handler probably
needs to be made, but I have not done that since I am unable to test any
changes to that.
Also re-order a couple of instructions to allow for delay with mfc0.

- Make cpu_switch() a normal call; formally it was splitted into halves.
- Fix an error in mips3_cpu_switch_resume(); ASID was not set correctly.
- Remove global variable 'curpcb' reference in mips1_proc_trampoline().
- Restore 'cpuregs.h'.

* Elimination of UADDR/KERNELSTACK

Affected files:
include/mips_param.h, include/pcb.h,
mips/locore_mips1.S, mips/locore_mips3.S,
mips/mips_machdep.c, mips/vm_machdep.c

Issue:

So far, NetBSD/mips has not successfully got rid of fixed-address
kernel stack. USPACE (two 4KB pages) of each process has two distinct
KSEG2 addresses, both refer to a single physical storage; one address
for fixed range [ UADDR .. KERNELSTACK ), and another for "normal" KSEG2
address which was allocated by kernel memory manager and unique to each
others of processes.

"Doubly mapped" USPACE complicates context switch. Both address ranges
have to be managed with a special care of "wired" TLB entries which
are never replaced until next context switch to ensure no TLB miss for
USPACE access. It's equally crumbersome that MIPS processor's cache
machinary gets be confused about USPACE contents because there are two
distinct KSEG2 addresses to manipulate one physical storage.

Solution:

Purge KERNELSTACK constant for kernel stack pointer and replace
it with process unique values. Kernel stack bottom is located at
'curproc->p_addr + USPACE'. Context switch is simplified as it unloads
half of TLB hardwiring burden. It just manages the unique KSEG2 address
of each USPACE to be wired. As the side effect, switch_exit() has no
MIPS processor ISA dependent code anymore. It switchs kernel stack to
proc0's USPACE which has KSEG0 address and no need of TLB entry.

* Extensive use of 'genassym.cf'

To hide target port dependent and/or processor register size dependent
constants from assembler routines, 'genassym.cf' now has an extentive
set of definitions for various constants and offset values of
structural objects. This change will contribute possible NetBSD/mips64
portability too.

* Separation and rename of locore_r2000/_r4000.S

Those files are now indepedent standalones from locore.S to ease
maintainance works, and renamed to match MIPS processor ISA version.

* Changes in kernel mode exception handlers

Kernel mode exception handlers hold exception contexts by pushing a
certain set of register values on stack for resuming kernel mode
processing. This context is now represented with 'struct trapframe',
which is smaller than full scale (user mode) exception context 'struct
frame'. Stack consumption of kernel mode exception services is now
similar to 4.4BSD/mips.

* Relocation of exception frame

User mode context 'struct frame' is moved to the very bottom of kernel
stack at 'curproc->p_addr + USPACE - sizeof(struct frame)' This change
saves a bit of instructions on every return to user processes as it
eliminates reference to global variable 'curpcb' each time.

* Refurblished DDB backtrace routine

It's a growing concern to maintain stacktrace() code correctly. It
could be simplified by enforcing special arrangements for some of
obscure locore routines which violate usual coding conventions.

New backtrace code searchs for certain instructions peculiar to any of
function tails. Specifically, "jr ra" for normal function returns, "jr
k0" for MIPS1 exception handlers and "eret" for MIPS3 handlers.

* Support for 64-bit safe user code
Affected Files:
${ARCH}/include/pubassym.cf lib/libc/arch/mips/gen/*setjmp*
include/setjmp.h mips/include/[lots] mips/mips/[lots]

Solution:

We define macros REG_L/REG_S and SZREG for loading and storing
registers and for the size of registers. The exact meaning
of these is controlled by a macro (currently _MIPS64) which
allows one to treat the registers as either 32-bit or 64-bit.
There are data types mips_reg_t and mips_fpreg_t which represent
the true register sizes, and avoid confusing register_t.

We needed a way to dynamically gen the structure sizes of things
like sigcontext for setjmp.h, so we defined a pubassym.cf for
libc routines like setjmp and longjmp.

NetBSD/mips allows ${ARCH}'s to be defined which preserve
all 64-bits of registers across user context switches. There
are still a few niceties to clean up for kernel mode context
switches.

* Support for QED 52xx processors
Affected Files:
mips/locore_mips3.S mips/pmap.c include/locore.h

Issue:
The QED 52xx family of processors are targeted at low cost
embedded systems, (i.e. CPUs ~$30) for systems like routers, printers,
etc. We have added preliminary support for some of the idiosyncrasies
of this processor, e.g. no L2 cache, etc. More work needs to be
done here because with a modest 2-way L1 cache, some of the rampant
flushing has significant performance implications. However,
it doesn't crash, which is a start.

Solution:
A routine for flushing the cache based on virtual addresses was added;
a routine which deals with the two-way set associativity of the
5230 L1 cache was added, accomodations to 5230's instruction hazards
were added.


* TLB Miss code for mips3/mips4 processors cleaned up significantly.
Affected Files:
mips/locore_mips3.S mips/vm_machdep.c include/locore.h mips_machdep.c
Issue:
The TLB Miss handler exceeded the allowed size, which wasn't
a problem because there was no handler for when the processor
was in 64-bit mode. The handler for invalid TLB exceptions
also appears to have much vestigial code, which made it
difficult to understand.

Solution:
Use the XCONTEXT register to store a pointer to the segment
map table, this coupled with removing some dead code allows
the handlers to fit.

branches: 1.1.2;
file locore_mips3.S was initially added on branch nisimura-pmax-wscons.

Sprinle RCSID

branches: 1.112.2;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

Fix logic inversion in 1.107

.set mips3 for __mips_o32
now o32 kernels boot again on my O2

Don't include <machine/param.h> in .S files, get the needed values from assym.h
Define NBPG as UL to avoid integer over with NBXSEG on LP64 systems.
(.S files don't like numbers with UL appended to them).

Define COP0 register that use select value in <mips/cpuregs.h>
Use those new definitions

On mipsNN use trap instructions when inconsistent status register settings
are found.

Don't compile the mips64 stuff if we being compiled as mips32

Don't .set mips3 if we are >= mips3 already
Use dins if we have it rather than two shifts.

In cpu_trampoline, load the ksp from the idlelwp after we enable KX.

Rework cavium support in preparation for MULTIPROCESSOR support

branches: 1.102.30;
Only jump through t9/ra (or k0) to help avoid hitting
the Loongson2 jump problem.

Add support for a loongson2_subr.S. This is needed since that chip needs
special handling to manually flush the ITLB on TLB updates.

More <machine/ include cleanup

Add mipsNN_cp0_watch{lo,hi}_{read,write}

Add separate support for MIPS32R2 and MIPS64R2.
Use EHB/SSNOP and jr.hb ra as appropriate (COP0_SYNC now uses them).
Add support for COP_0_HWRENA and COP_0_USERLOCAL (use by rdhwr $3,$29
instruction for TLS support).
Add mips3+ reserved instruction handler to emulate rdhwr is many fewer
instructions.

Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU

branches: 1.96.4; 1.96.6; 1.96.8;
Merge from matt-nb5-mips64
Merge mips-specific arch files.

Rename L_ADDR to L_PCB and amend some comments accordingly.

- Use uvm_lwp_setuarea() instead of directly setting address to lwp_t::l_addr.
- Replace most remaining uses of l_addr with uvm_lwp_getuarea() or lwp_getpcb().
- Amend assembly in ports where it accesses PCB via struct user.
- Rename L_ADDR to L_PCB in few places. Reduce sys/user.h inclusions.

branches: 1.93.20; 1.93.38;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.92.2; 1.92.10;
Fix typo.

merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.

branches: 1.90.4; 1.90.6; 1.90.12;
uvm.page_idle_zero now is a bool, not a 32bit value any more.

BTW, is it still worth to have uvm_pageidlezero()? Which port uses it?

branches: 1.89.2;
Merge newlock2 to head.

branches: 1.88.20;
merge ktrace-lwp.

Add mips3_cp0_pg_mask_write() to initialize pagemask register.

branches: 1.86.6; 1.86.14; 1.86.16;
Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.

branches: 1.85.2;
Merge the nathanw_sa branch.

branches: 1.84.4;
Sprinkle a little more COP0_SYNC (in an unused function...).

In the idle functions, set curproc to NULL and (#ifdef LOCKDEBUG) call
sched_unlock_idle before enabling interrupts. LOCKDEBUG kernels now
boot successfully.

Thanks to Chris Gilbert for helping fix this.

Include "opt_lockdebug.h" here to #ifdef LOCKDEBUG actually does something.

Fix tyop.

White space nits.

Use CPU_MIPS_USE_WAIT and CPU_MIPS_NO_WAIT in the CPU table, and use
the generic name "mips_wait_idle" for the old function that had both
rm52xx_idle and mipsNN_idle entry points.

Remove some unnecessary nops after some mfc0's.

branches: 1.77.4;
make this compile and work with MIPS3_5900.

Add support for MIPS32 and MIPS64 architectures:
- Remove all mmu-related code that may use 32 register on mips32-style
implementatios and move them to mipsX_subr.S - which is then included
from mips{3,32,64,5900}_subr.S with various control defines enabled.
- Remove local cache instruction flags
- Add badaddr64 (from Broadcom Corp).

add #ifdef DEBUG around VCED_count etc.

split VCED and VCEI.

simplify VCED processing.
just write back and invalidate secondary cache line and fetch data again.

branches: 1.72.2;
Merge the thorpej-mips-cache branch onto the trunk. This is an
overhaul of how caches are handled for NetBSD's MIPS ports.

branches: 1.71.2;
R5900 support.
COP0_SYNC
In R5900 mtc0, tlbr, tlbp, tlbwi, tlbwr must be followed by sync.p.
if defined MIPS3_5900, COP0_SYNC is defined as sync.p. else nothing.
IPL_ICU_MASK
mask interrupt directly ICU instead of SR.IM.
I've added this feature to support software interrupt for R5900.
and this option may be useful for platform which has cascaded ICU.

Fix bug in mips3_proc_trampoline: SR wasn't disabled on entry, allowing an
interrupt to sneak in after EXL had been set; the interrupt EPC was stale
as PC isn't saved if EXL is set, causing the eret to return to the wrong
place and leading to kernel-mode TLB misses on user addresses. The bug
was discovered by the japanese NetBSD/*mips folks and the same fix was
found independently by shinohara-san (shin@netbsd.org).

branches: 1.69.2;
Always indirect through the "locoresw" to get the cache ops, since
there are just far too many combinations to handle with magic
#ifdefs in any sane way. Also, add a HitFlushDCache op to the
"locoresw", and fill it in as appropriate (it's NULL on MIPS-I,
so watch out).

These changes ensure that my R4600 Indy (with 2-way cache) gets
the correct cache ops when the kernel is built with only MIPS3
support, resulting in a kernel that is significantly more stable.

add missing #include "opt_kgdb.h"

Add an idle loop routine for the QED RM52xx family. This uses the
RM52xx `wait' insn to power down the pipeline.

branches: 1.66.2;
Fix register name typo.

New syscall entry implementation based on the Alpha version
as hacked by mycroft.
- Use syscall_intern() to give a process a plain or fancy
syscall based on ktrace flags.
- Avoid copying from the trapframe into a local array as much
as possible.

Yields roughly 5% improvement on a 25MHz R3000 (DECstation 5000/200)
on a simple syscall benchmark.

There's still some work that can be done using __HAVE_MINIMAL_EMUL.

Make the astpending flag per-process.

Check for ASTs in Syscall and UserGenException, too; AST processing
must be done on *every* return to userland.

Hook mips3 cache error vector. No real handler, only set-up for a panic.
A real handler is hard.

For MIPS software masking option, when returning to user mode apply
the mask to all interrupts to catch changes in the mask state faster.
Does not affect platforms w/o this option enabled.

Use only one TLB entry to wire down process's USPACE since it's
now guranteed to be aligned on 8KB boundary in kernel virutal
address. Retain one more free TLB entry.

fix cp0 hazard.
R4000 requires 3 nops between tlbr and dmfc0.

In mips3_TBIS(va) do not invalidate the other half of the JTLB entry if
the page is wired down. Flushing both halves of a wired TLB entry resulted
in hangs when in programs called for and released kernel memory
soon after being invoked. In particular, we see this when single-stepping
a process using GDB.

It would be better if we could arrange to use both halves of the TLB
entry for the PCB, but for some reason we frequently end up with things
on an odd page boundary.

clean up and consistency for CP0 Count, Compare, Wired, and Config
access function names and prototypes.

nuke mips3_clearBEV(). There's really no point in coding a
special-purpose assembly routine for things like this.

provide mips3_ld() and mips3_sd(), functions which provide safe wrappers
for mips3 (and later) 'ld' and 'sd' instructions. These currently
only are properly implemented for the _MIPS_BSD_API_LP32 and
_MIPS_BSD_API_LP32_64CLEAN 'API's. They're pretty messy, but when you
need them, you really need them.

No longer save $at on syscall entry. v1 does appear to be used as if
you do not save it and pass it along in rval the system will start
to fail running user programs. This finishes the suggestion by cgd to
not save some registers on syscall entry.

Re-enable SR IE bit before calling syscall(). Matches Tohru's mips1 change.

Do not save t* registers in syscall stub as suggested by cgd. Saves
a whole 0.01us in lmbench lat_syscall null on our 250Mhz QED system.
$at is still saved just to be safe, although it looks like it does
not need to be. $v1 is used in syscall(), although I'm not sure why.

Introduce 'segbase' global variable to hold the pointer to current
process's segtab, retiring 'pcb_segtab' field from 'struct pcb'.
This would be another MULTIPROCESSOR unfriendly and the necessity
might be eliminated when the way to hold PTE is redesigned.

modify mips3 locore to elminate the abuse of XContext
so that we can run on systems that do not have XContext
(e.g. IDT 32364).

Remove old comment.

In outofworld, keep $sp for DDB case if it looks like a kernel address
so the stacktrace is ok.