#define<tab>
Nuke trailing whitespace.

Use proper "page" alignments for R5k Page Invalidate(S) op. PR/55139

According to NEC "User's Manual VR5000, VR1000 64-BIT MICROPROCESSOR
INSTRUCTION" (U12754EJ1V0UMJ1), R5000 Page Invalidate (S) op does
"a page invalidate by doing a burst of 128 line invalidates to
the secondary cache at the page specified by the effective address
generated by the CACHE instruction, which must be page aligned."

This description looks a bit confusing, but "page" used here
implies fixed 32 byte cacheline * 128 lines == 4096 bytes,
not our variable "PAGE_SIZE" used in VM paging ops. Note
the current default PAGE_SIZE for MIPS3 has been changed to 8192.

While here, also define and use proper macro for the "page" and CACHEOP
arg for the R5k Page_Invalidate_S op, as the manual also describes
the cache op field 10111 as "Page Invalidate" for the secondary cache.

No visible regression on Cobalt Qube 2700 (Rm5230) through
whole installation using netbsd-9 based Cobalt RestoreCD/USB.

branches: 1.4.22;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

branches: 1.3.96; 1.3.122; 1.3.142;
merge ktrace-lwp.

Add prototype for r5k_sdcache_wbinv_range_index()

branches: 1.1.2;
Add support for R5k secondary caches, from code Chris Sekiya sent me a long
time ago, with small tweaks by me. Since the R5k doesn't do VCE, the pmap
still needs to be whacked for R5kSC CPUs to work correctly, but this is a
start.

Use proper "page" alignments for R5k Page Invalidate(S) op. PR/55139

According to NEC "User's Manual VR5000, VR1000 64-BIT MICROPROCESSOR
INSTRUCTION" (U12754EJ1V0UMJ1), R5000 Page Invalidate (S) op does
"a page invalidate by doing a burst of 128 line invalidates to
the secondary cache at the page specified by the effective address
generated by the CACHE instruction, which must be page aligned."

This description looks a bit confusing, but "page" used here
implies fixed 32 byte cacheline * 128 lines == 4096 bytes,
not our variable "PAGE_SIZE" used in VM paging ops. Note
the current default PAGE_SIZE for MIPS3 has been changed to 8192.

While here, also define and use proper macro for the "page" and CACHEOP
arg for the R5k Page_Invalidate_S op, as the manual also describes
the cache op field 10111 as "Page Invalidate" for the secondary cache.

No visible regression on Cobalt Qube 2700 (Rm5230) through
whole installation using netbsd-9 based Cobalt RestoreCD/USB.

Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

branches: 1.3.96; 1.3.122; 1.3.142;
merge ktrace-lwp.

Add prototype for r5k_sdcache_wbinv_range_index()

branches: 1.1.2;
Add support for R5k secondary caches, from code Chris Sekiya sent me a long
time ago, with small tweaks by me. Since the R5k doesn't do VCE, the pmap
still needs to be whacked for R5kSC CPUs to work correctly, but this is a
start.

Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

branches: 1.3.96; 1.3.142;
merge ktrace-lwp.

Add prototype for r5k_sdcache_wbinv_range_index()

branches: 1.1.2;
Add support for R5k secondary caches, from code Chris Sekiya sent me a long
time ago, with small tweaks by me. Since the R5k doesn't do VCE, the pmap
still needs to be whacked for R5kSC CPUs to work correctly, but this is a
start.