History log of /netbsd-current/sys/arch/arm/sunxi/sunxi_ccu_display.c
Revision (<<< Hide revision tags) (Show revision tags >>>) Date Author Comments
# 1.3 03-Aug-2023 mrg

avoid potentially uninitialised variable that likely won't happen.

GCC 12 can't tell that hardware / platform design means it won't happen.


Revision tags: netbsd-10-base bouyer-sunxi-drm-base netbsd-9-3-RELEASE thorpej-i2c-spi-conf2-base thorpej-futex2-base thorpej-cfargs2-base cjep_sun2x-base1 cjep_sun2x-base cjep_staticlib_x-base1 netbsd-9-2-RELEASE cjep_staticlib_x-base thorpej-i2c-spi-conf-base thorpej-cfargs-base thorpej-futex-base netbsd-9-1-RELEASE bouyer-xenpvh-base2 phil-wifi-20200421 bouyer-xenpvh-base1 phil-wifi-20200411 bouyer-xenpvh-base is-mlppp-base phil-wifi-20200406 ad-namecache-base3 netbsd-9-0-RELEASE netbsd-9-0-RC2 ad-namecache-base2 ad-namecache-base1 ad-namecache-base netbsd-9-0-RC1 phil-wifi-20191119 netbsd-9-base phil-wifi-20190609 isaki-audio2-base pgoyette-compat-20190127 pgoyette-compat-20190118 pgoyette-compat-1226 pgoyette-compat-1126 pgoyette-compat-1020 pgoyette-compat-0930 pgoyette-compat-0906 pgoyette-compat-0728 phil-wifi-base pgoyette-compat-0625 pgoyette-compat-0521 pgoyette-compat-0502 pgoyette-compat-0422 pgoyette-compat-0415 pgoyette-compat-0407
# 1.2 02-Apr-2018 bouyer

branches: 1.2.2;
- sunxi_ccu_lcdxch1_set_rate(): enable parent before calling
sunxi_ccu_div_set_rate(). If it's not enabled get_rate() will return 0 and
sunxi_ccu_div_set_rate() will fail.
- rework sunxi_ccu_lcdxch0_set_rate() to actually really select the best
parent.


# 1.1 01-Apr-2018 bouyer

Add a round_rate() callback for the sunxi clock domain.
Add a sunxi_ccu_display.c file with helpers for setting up display engine
clocks.
for fractional clocks, rename frac_en to div_en, I got the logic inverted.
Adjust tcon0-ch0, tcon0-ch1, tcon1-ch0 and tcon1-ch1 definitions to
automatically select a parent. tcon0 hardcoded to pll3 and tcon1 to pll7.
Define a round_rate() callback for these clocks, as well as fractional clocks.
Hardcode debe clocks parent to pll5.