Support PMAP_FAULTINFO on arm

Remove port-acorn26

OK core@

Don't include <machine/fp.h> since it no longer exists

Remove pcb_fpstate.
Add pcb_kernel_vfp.

Rename pcb_sp/PCB_SP to pcb_ksp/PCB_KSP so that ipsec.c will compile.

branches: 1.24.2;
small rototill.
pcb_flags is dead. PCB_NOALIGNFLT is now in stored l_md.md_flags as
MDLWP_NOALIGNFLT. This avoids a few loads of the PCB in exception handling.
pcb_tf has been moved to l_md.md_tf. Again this avoids a lot of pcb
references just to access or set this. It also means that pcb doesn't
need to accessed by MI code.
Move pcb_onfault to after the pcb union.
Add pcb_sp macro to make code prettier.
Add lwp_settrapframe(l, tf) to set the l_md.md_tf field.
Use lwp_trapframe to access it (was process_frame but that name was changed
in a previous commit).
Kill off curpcb in acorn26.
Kill the checks for curlwp being NULL.
Move TRAP_USERMODE from arm32/fault.c to frame.h and a __PROG26 version.
Replace tests for usermode with that macro.

Kill curpcb/ci_curpcb. Use device_t in cpu_info.
Add ci_softc (where ci_curpcb was so cpu_info doesn't change).

Rework VFP support to use PCU.
Add emulation of instruction which save/restore the VFP FPSCR.
Add a sysarch hook to VFP FPSCR manipulation.

[The emulation will be used by libc to store/fetch exception modes and
rounding mode on a per-thread basis.]

Update comment.

branches: 1.20.4; 1.20.12;
Add a define for pcb_user_pid_rw

branches: 1.19.18; 1.19.22; 1.19.28;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.18.2; 1.18.4;
VFP support.

branches: 1.17.2; 1.17.6;
With the removal of IPKDB on arm, the undefined stack is only used to
bounce into SVC32 mode, there is no per-process data stored on it.

We can therefore use the undefined stack setup by the platform machdep.c
as a system wide undefined stack.

This removes the need for a per-process undefined stack, and the processor
mode switching overhead it causes in cpu_switchto.

The space freed in the USPACE is used to increase the per process kernel
stack size.

branches: 1.16.2; 1.16.8;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

ARM cpu_switchto() has been partially broken since yamt-idlelwp was merged
as its cache/tlb management smarts relied too heavily on pre-merge context-
switch behaviour. See PR kern/36548 for one manifestation of the breakage.

To address this:
- Ditch the shadow pmap variables in the PCB (pagedir, l1vec, dacr, cstate)
as it was too easy for them to get out of sync with the pmap.
- Re-write (and fix) the convoluted cpuswitch.S cache/tlb ASM code in C.
It's only slightly less efficient, but is much more readable/maintainable.
- Document cpufuncs.cf_context_switch() as being C-callable.
- pmap_activate() becomes a no-op if the lwp's vmspace is already active.
(Good performance win, since pmap_activate() is now invoked on every
context-switch, even though ARM's cpu_switchto() already does all the
grunt work)

XXX: Some CPU-specific armXX_context_switch() implementations (arm67,
arm7tdmi, arm8) always flush the I+D caches. This should not be necessary.
Someone with access to hardware (acorn32?) needs to deal with this.

branches: 1.14.2; 1.14.10; 1.14.16; 1.14.18; 1.14.20; 1.14.22;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

branches: 1.13.4;
- Document COMPAT_15 as doing nothing
- Add COMPAT_15 to all the kernel that had COMPAT_14, for the sake of coherency
- Remove the only occurences of #ifdef COMPAT_15 in the tree: for the ARM
ports, COMPAT_15 was always used in conjunction with EXEC_AOUT. Only EXEC_AOUT
matters here.

This address kern/18407

branches: 1.12.20; 1.12.22;
merge ktrace-lwp.

branches: 1.11.16;
Enable alignment faults on arm32 for both kernel and userland.

If COMPAT_15 and EXEC_AOUT are defined, support per-process
alignment checking where AFLTs are always enabled when running
kernel code and userland ELF binaries, and dynamically disabled/
enabled when switching to/from a.out binaries. This is necessary
in order to execute older a.out binaries, where gcc made
deliberate use of misaligned loads under certain circumstances.

Document the need for pcb32_r8 to be quad-aligned, now that cpuswitch()
uses Xscale's "strd" instruction.

branches: 1.9.2;
Remove #ifdefs supporting the old pmap, switching fully to the new.

Add the generic arm32 bits of the new pmap, contributed by Wasabi Systems.

Some features of the new pmap are:

- It allows L1 descriptor tables to be shared efficiently between
multiple processes. A typical "maxusers 32" kernel, where NPROC is set
to 532, requires 35 L1s. A "maxusers 2" kernel runs quite happily
with just 4 L1s. This completely solves the problem of running out
of contiguous physical memory for allocating new L1s at runtime on a
busy system.

- Much improved cache/TLB management "smarts". This change ripples
out to encompass the low-level context switch code, which is also
much smarter about when to flush the cache/TLB, and when not to.

- Faster allocation of L2 page tables and associated metadata thanks,
in part, to the pool_cache enhancements recently contributed to
NetBSD by Wasabi Systems.

- Faster VM space teardown due to accurate referenced tracking of L2
page tables.

- Better/faster cache-alias tracking.

The new pmap is enabled by adding options ARM32_PMAP_NEW to the kernel
config file, and making the necessary changes to the port-specific
initarm() function. Several ports have already been converted and will
be committed shortly.

Change pcb32_pagedir to a paddr_t (after all, it's used as a paddr_t
everywhere in the code).

branches: 1.6.2;
Undo recent cpu_switch register usage changes in order to decrease nathanw_sa
merge pain.

In cpu_switch(), stack more registers at the start of the function,
and hence save fewer into the PCB. This should give me enough free
registers in cpu_switch to tidy things up and support MULTIPROCESSOR
properly. While we're here, make the stacked registers into an
APCS stack frame, so that DDB backtraces through cpu_switch() will
work.

This also affects cpu_fork(), which has to fabricate a switchframe and
PCB for the new process.

Move curpcb into struct cpu_info in MULTIPROCESSOR kernels.

- Move more contents of various <machine/vmparam.h> files into
<arm/arm32/vmparam.h> (mostly the stuff that's tied to the pmap
implementation).
- Since the MMU definitions in pte.h are specific to ARM processors
that support 32-bit mode, move pte.h to <arm/arm32/pte.h>.
- Make the Netwinder startup file build again (use PT_B|PT_C, rather
than PT_CACHEABLE, since the latter expands to a variable these days).

branches: 1.2.2; 1.2.6;
Don't define pcb_* register macros.
pcb_sp macro conflicts with sys/netinet6/ipsec.c.

branches: 1.1.2;
Add a merged <pcb.h> for arm26/arm32.

Remove port-acorn26

OK core@

Don't include <machine/fp.h> since it no longer exists

Remove pcb_fpstate.
Add pcb_kernel_vfp.

Rename pcb_sp/PCB_SP to pcb_ksp/PCB_KSP so that ipsec.c will compile.

branches: 1.24.2;
small rototill.
pcb_flags is dead. PCB_NOALIGNFLT is now in stored l_md.md_flags as
MDLWP_NOALIGNFLT. This avoids a few loads of the PCB in exception handling.
pcb_tf has been moved to l_md.md_tf. Again this avoids a lot of pcb
references just to access or set this. It also means that pcb doesn't
need to accessed by MI code.
Move pcb_onfault to after the pcb union.
Add pcb_sp macro to make code prettier.
Add lwp_settrapframe(l, tf) to set the l_md.md_tf field.
Use lwp_trapframe to access it (was process_frame but that name was changed
in a previous commit).
Kill off curpcb in acorn26.
Kill the checks for curlwp being NULL.
Move TRAP_USERMODE from arm32/fault.c to frame.h and a __PROG26 version.
Replace tests for usermode with that macro.

Kill curpcb/ci_curpcb. Use device_t in cpu_info.
Add ci_softc (where ci_curpcb was so cpu_info doesn't change).

Rework VFP support to use PCU.
Add emulation of instruction which save/restore the VFP FPSCR.
Add a sysarch hook to VFP FPSCR manipulation.

[The emulation will be used by libc to store/fetch exception modes and
rounding mode on a per-thread basis.]

Update comment.

branches: 1.20.4; 1.20.12;
Add a define for pcb_user_pid_rw

branches: 1.19.18; 1.19.22; 1.19.28;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.18.2; 1.18.4;
VFP support.

branches: 1.17.2; 1.17.6;
With the removal of IPKDB on arm, the undefined stack is only used to
bounce into SVC32 mode, there is no per-process data stored on it.

We can therefore use the undefined stack setup by the platform machdep.c
as a system wide undefined stack.

This removes the need for a per-process undefined stack, and the processor
mode switching overhead it causes in cpu_switchto.

The space freed in the USPACE is used to increase the per process kernel
stack size.

branches: 1.16.2; 1.16.8;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

ARM cpu_switchto() has been partially broken since yamt-idlelwp was merged
as its cache/tlb management smarts relied too heavily on pre-merge context-
switch behaviour. See PR kern/36548 for one manifestation of the breakage.

To address this:
- Ditch the shadow pmap variables in the PCB (pagedir, l1vec, dacr, cstate)
as it was too easy for them to get out of sync with the pmap.
- Re-write (and fix) the convoluted cpuswitch.S cache/tlb ASM code in C.
It's only slightly less efficient, but is much more readable/maintainable.
- Document cpufuncs.cf_context_switch() as being C-callable.
- pmap_activate() becomes a no-op if the lwp's vmspace is already active.
(Good performance win, since pmap_activate() is now invoked on every
context-switch, even though ARM's cpu_switchto() already does all the
grunt work)

XXX: Some CPU-specific armXX_context_switch() implementations (arm67,
arm7tdmi, arm8) always flush the I+D caches. This should not be necessary.
Someone with access to hardware (acorn32?) needs to deal with this.

branches: 1.14.2; 1.14.10; 1.14.16; 1.14.18; 1.14.20; 1.14.22;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

branches: 1.13.4;
- Document COMPAT_15 as doing nothing
- Add COMPAT_15 to all the kernel that had COMPAT_14, for the sake of coherency
- Remove the only occurences of #ifdef COMPAT_15 in the tree: for the ARM
ports, COMPAT_15 was always used in conjunction with EXEC_AOUT. Only EXEC_AOUT
matters here.

This address kern/18407

branches: 1.12.20; 1.12.22;
merge ktrace-lwp.

branches: 1.11.16;
Enable alignment faults on arm32 for both kernel and userland.

If COMPAT_15 and EXEC_AOUT are defined, support per-process
alignment checking where AFLTs are always enabled when running
kernel code and userland ELF binaries, and dynamically disabled/
enabled when switching to/from a.out binaries. This is necessary
in order to execute older a.out binaries, where gcc made
deliberate use of misaligned loads under certain circumstances.

Document the need for pcb32_r8 to be quad-aligned, now that cpuswitch()
uses Xscale's "strd" instruction.

branches: 1.9.2;
Remove #ifdefs supporting the old pmap, switching fully to the new.

Add the generic arm32 bits of the new pmap, contributed by Wasabi Systems.

Some features of the new pmap are:

- It allows L1 descriptor tables to be shared efficiently between
multiple processes. A typical "maxusers 32" kernel, where NPROC is set
to 532, requires 35 L1s. A "maxusers 2" kernel runs quite happily
with just 4 L1s. This completely solves the problem of running out
of contiguous physical memory for allocating new L1s at runtime on a
busy system.

- Much improved cache/TLB management "smarts". This change ripples
out to encompass the low-level context switch code, which is also
much smarter about when to flush the cache/TLB, and when not to.

- Faster allocation of L2 page tables and associated metadata thanks,
in part, to the pool_cache enhancements recently contributed to
NetBSD by Wasabi Systems.

- Faster VM space teardown due to accurate referenced tracking of L2
page tables.

- Better/faster cache-alias tracking.

The new pmap is enabled by adding options ARM32_PMAP_NEW to the kernel
config file, and making the necessary changes to the port-specific
initarm() function. Several ports have already been converted and will
be committed shortly.

Change pcb32_pagedir to a paddr_t (after all, it's used as a paddr_t
everywhere in the code).

branches: 1.6.2;
Undo recent cpu_switch register usage changes in order to decrease nathanw_sa
merge pain.

In cpu_switch(), stack more registers at the start of the function,
and hence save fewer into the PCB. This should give me enough free
registers in cpu_switch to tidy things up and support MULTIPROCESSOR
properly. While we're here, make the stacked registers into an
APCS stack frame, so that DDB backtraces through cpu_switch() will
work.

This also affects cpu_fork(), which has to fabricate a switchframe and
PCB for the new process.

Move curpcb into struct cpu_info in MULTIPROCESSOR kernels.

- Move more contents of various <machine/vmparam.h> files into
<arm/arm32/vmparam.h> (mostly the stuff that's tied to the pmap
implementation).
- Since the MMU definitions in pte.h are specific to ARM processors
that support 32-bit mode, move pte.h to <arm/arm32/pte.h>.
- Make the Netwinder startup file build again (use PT_B|PT_C, rather
than PT_CACHEABLE, since the latter expands to a variable these days).

branches: 1.2.2; 1.2.6;
Don't define pcb_* register macros.
pcb_sp macro conflicts with sys/netinet6/ipsec.c.

branches: 1.1.2;
Add a merged <pcb.h> for arm26/arm32.