Provide a shared pmap_devmap implementation and convert all pmap_devmap
arrays to use DEVMAP_ENTRY{,_END}

MI PMAP EFI_RUNTIME support

Update to support EFI runtime outside the kernel virtual address space
by creating an EFI RT pmap that can be activated / deactivated when
required.

Adds support for EFI RT to ARM_MMU_EXTENDED (ASID) 32-bit Arm machines.

On Arm64 the usage of pmapboot_enter is reduced and the mappings are
created much later in the boot process -- now in cpu_startup_hook.
Backward compatiblity for KVA mapped RT from old bootaa64.efi is
maintained.

Adding support to other platforms should be easier as a result.

Arm: Add support for SMC Calling Convention

Arm DEN0028 defines a calling mechanism used with Secure Monitor Call (SMC)
and Hypervisor Call (HVC) instructions. To discover SMCCC, we must:

1) Find the PSCI conduit (either via ACPI FADT, or Device Tree)
2) Use PSCI_VERSION to determine whether PSCI_FEATURES is supported
3) Call PSCI_FEATURES with SMCCC_VERSION to determine the implementation
version.

make process_machdep.c included always since it provides register i/o used by
sys_process_getlwpstatus.c which is always included.

harmonize process_machdep.c inclusion.

Collapse all CPU_CORTEXA<n> options into CPU_CORTEX and do runtime
detection instead of ifdefs where required.

Add support for Privileged Access Never (ARMv8.1-PAN).

PAN provides the same functionality as SMAP on x86: it forbids kernel
access to userland pages when PSTATE.PAN=1, and allows such accesses when
PSTATE.PAN=0.

We clear SCTLR_SPAN, to guarantee that PAN=1 each time the kernel is
entered. We catch PAN faults and panic right away without further
processing. In copyin, copyout, etc, we temporarily authorize access to
userland pages.

PAN is a very useful exploit mitigation. Reviewed by ryo@, thanks. Tested
on Qemu. Enabled by default.

Enable ChaCha NEON code on armv7 too.

The 4-blocks-at-a-time assembly helper is disabled for now; adapting
it to armv7 is going to be a little annoying with only 16 128-bit
vector registers.

(Should also do a fifth block in the integer registers for 320 bytes
at a time.)

Fix outdated comment.

New permutation-based AES implementation using ARM NEON.

Also derived from Mike Hamburg's public-domain vpaes code.

PMAP_DEBUG has been deleted on arm

Add KASAN-DMA support on aarch64, same as amd64. Discussed with skrll@.

Add support for Branch Target Identification (BTI).

On the executable pages that have the GP (Guarded Page) bit, the semantic
of the "br" and "blr" instructions is changed: the CPU expects the first
instruction of the jump/call target to be "bti", and faults if it isn't.

We add the GP bit on the kernel .text pages (and incidentally the .rodata
pages, but we don't care). The compiler adds a "bti c" instruction at the
beginning of each C function. We modify the ENTRY() macros to manually add
"bti c" in the asm functions.

cpuswitch.S needs a specific change: with "br x27" the CPU expects "bti j",
which is bad because the functions begin with "bti c"; switch to "br x16",
for the CPU to accept "bti c".

BTI helps defend against JOP/COP. Tested on Qemu.

Add support for Pointer Authentication (PAC).

We use the "pac-ret" option, to sign the return instruction pointer on
function entry, and authenticate it on function exit. This acts as a
mitigation against ROP.

The authentication uses a per-lwp (secret) I-A key stored in the 128bit
APIAKey register and part of the lwp context. During lwp creation, the
kernel generates a random key, and during context switches, it installs
the key of the target lwp on the CPU.

Userland cannot read the APIAKey register directly. However, it can sign
its pointers with it, because the register is architecturally shared
between userland and the kernel. Although part of the CPU design, it is
a bit of an undesired behavior, because it allows to forge valid kernel
pointers from userland. To avoid that, we don't share the key with
userland, and rather switch it in EL0<->EL1 transitions. This means that
when userland executes, a different key is loaded in APIAKey than the one
the kernel uses. For now the userland key is a fixed 128bit zero value.

The DDB stack unwinder is changed to strip the authentication code from
the pointers in lr.

Two problems are known:

* Currently the idlelwps' keys are not really secret. This is because
the RNG is not yet available when we spawn these lwps. Not overly
important, but would be nice to fix with UEFI RNG.
* The key switching in EL0<->EL1 transitions is not the most optimized
code on the planet. Instead of checking aarch64_pac_enabled, it would
be better to hot-patch the code at boot time, but there currently is
no hot-patch support on aarch64.

Tested on Qemu.

branches: 1.153.4;
Various updates and improvements to cpu start up on arm/aarch64

- start sharing more code around the AP startup messaging.
- call arm_cpu_topology_set early so that ci_core_id is available for
drivers, e.g. bcm2835_intr.c
- both arm and aarch64 now have
- a static cpu_info_store array
- the same arm_cpu_{hatched,mbox}

Sort a bit

Trailing whitespace

port the arm64 cpu topology setup for big.little to arm.

rename arm64 cpu_do_topology() to arm_cpu_do_topology() and
call it from both arm cpu_attach().

replace both aarch64_set_topology() inline code in arm
cpu_attach() with new arm_cpu_do_topology(), which is called
by the arm64 locore as well (possibly not needed, which would
allow it to become static.)

not yet tested on a real big.little armv7 system. tested
on rockpro64 and pinebook pro.

branches: 1.149.2;
Move all non-emulation-specific coredump code into the coredump module,
and remove all #ifdef COREDUMP conditional compilation. Now, the
coredump module is completely separated from the emulation modules, and
they can all be independently loaded and unloaded.

Welcome to 9.99.18 !

Merge the [pgoyette-compat] branch

Split armv7/armv8 tprof backend config logic from the fdt bus glue.

Add support for EFI runtime services on aarch64.

Provide generic start code that assumes the MMU is off and caches are
disabled as per the linux booting protocol for ARMv6 and ARMv7 boards.
u-boot image type should be changed to 'linux' for correct behaviour.

The new start code builds a minimal "bootstrap" L1PT with cached access
disabled and uses the same table for all processors. AP startup is
performed in less steps and more code is written in C.

The bootstrap tables and stack are placed into an (orphaned) section
"_init_memory" which is given to uvm when it is no longer used.

Various kernels have been converted to use this code and tested. Some
boards were provided by TNF. Thanks!

The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS
kernels. The GENERIC kernel will also work on RPI2 using u-boot.

Thanks to martin@ and aymeric@ for testing on parallella and nanosoc
respectively

Whitespace

Centralise defparam CONSADDR, CONSPEED, CONMODE and CONADDR into
opt_console.h and adjust.

Whitespace

remove reference to CPU_ARMV2, suggested by jmcneill@

Retire CPU_ARM2, CPU_ARM250 and CPU_ARM3, they are all leftovers of
acorn26.

ok jmcneill@ skrll@

branches: 1.139.2;
Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

branches: 1.138.2;
Remove port-acorn26

OK core@

G/C ARM32_NEW_VM_LAYOUT

Add CPU_CORTEXA35

defflag CPU_CORTEXA53

Add __HAVE_GENERIC_CPU_INITCLOCKS option. If set, don't export
cpu_initclocks from device drivers as common code (in this case FDT) will
provide its own copy.

Add support for ARM Power State Coordination Interface (PSCI).

branches: 1.132.2;
Recognize Cortex-A57 FPU, GIC, and Generic Timer.

Support pmap_pv_track and friends

According to the Cortex-A5 TRM, the CBAR register is not implemented and
always reads as 0x00000000. Add ARM_CBAR option to set this in kernel
config.

Add CPU_CORTEXA17

branches: 1.128.2;
Add option ARM_HAS_LPAE

branches: 1.127.2;
Support (untested) SHEEVA_L2_CACHE and SHEEVA_L2_CACHE_WT options.
Move prototypes out to <arm/cpufunc.h> to their own file.
Add sdcache routines to cpufunc_asm_sheeva.S
Add code sheeve_setup to init the sdcache and sdcache info.

branches: 1.126.2;
Make the ARM pmap use ASIDs, split TTBRs, and MP safe. This only happens for
ARMv6 or later CPUs. This means that on context switch that the TLBs and
caches no longer to cleaned/flushed. Also, eXecute Never (XN) protection has
been added so non-exec pages can not be run. Change the page size for ARMv6+
to be 8KB while allows a L1PT to be a normal page. This means that the L1PT
is not special. Use the XN support to only sync pages that are executed from.

defflag VERBOSE_INIT_ARM

cpu_cortex doesn't need the arm11 cpufuncs any more

CPU_ARMV[67] imply ARM32_DISABLE_ALIGNMENT_FAULTS
Make it explicit.

Nuke atomic.S since we have MI defined atomic ops

Rework to have CPU_PREARMV6, CPU_ARMV6, as well as CPU_ARMV7

branches: 1.120.2;
File VBAR option

Add a ARM_HAS_VBAR option which forces the use of the VBAR register. This
allows much code to deal with vector_page mappings to be eliminated. On a
BEAGLEBONE kernel, this saves 8KB of text and instructions that never have
to be executed. (The PJ4B has VBAR but doesn't implement the security
extensions it is part of so a method was needed to allow it use VBAR with
relying on the default test for the security extensions.)

Add CPU_ARMV7 and make CPU_PJ4B and CPU_CORTEX instantiate it.

Make PJ4B support code compilable.

Obtained from Marvell, Semihalf.

Add BUSDMA_COUNTERS option

Disable bzero_page_vfp and bcopy_page_vfp since it really isn't any faster
than memcpy.

Add code to use VFP(or Neon) instructions to zero or copy a page via
pmap_zero_page and pmap_copy_page. (Not hooked into vfp_init yet).
Requires FPU_VFP

ARMFPE hasn't compiled since NetBSD 4. Remove it.
Complete support for FPU_VFP.
fpregs now contains vfpreg.
XXX vfpreg only has space for 16 64-bit FP registers though VFPv3 and later
have 32 64-bit FP registers.

Add a PMAP_NEEDS_ALLOC_POOLPAGE / PMAP_ALLOC_POOLPAGE hook so systems can
allocate pool pages from a specific VM freelist.

add _ARM32_NEED_BUS_DMA_BOUNCE to opt_arm_bus_space.h (It's not really a
bus_space option but it's close enough).

branches: 1.110.2;
Add core locator to mainbus. Add support for attaching multiple CPUs

Rename ARM options PROCESS_ID_IS_CUR{CPU,LWP} to TPIDRPRW_IS_CUR{CPU,LWP}
since TPIDRPRW is the cp15 register name.
Initialize it early in start along with CI_ARM_CPUID.
Remove other initializations.
We alays have ci_curlwp.
Enable TIPRPRW_IS_CURCPU in std.beagle.
[tested on a beaglboard (cortex-a8)]

Rework VFP support to use PCU.
Add emulation of instruction which save/restore the VFP FPSCR.
Add a sysarch hook to VFP FPSCR manipulation.

[The emulation will be used by libc to store/fetch exception modes and
rounding mode on a per-thread basis.]

COMPAT_NETBSD32 support for ARM. Which is strange since ARM is already
32-bits. But the newer ARM ABI AAPCS changes the alignment of 64-bit
fields so structures need to copied in and out to deal with the alignment
change. This is a kludge but makes debugging of AAPCS support much easier.

Add support for the ARM1176JZS

Add intrbase locator to mainbus.

Begin support for Cortex A5, A7, A15 and expand A8 and A9 definitions.
Instead of testing all possible CPUids for a cortex, we know what range
a cortex will be so mask out the insignificant parts and do a single test.

branches: 1.103.2;
Require arm3_cache_flush for ARM2/ARM250.

branches: 1.102.2; 1.102.6;
Welcome to 5.99.53! Merge rmind-uvmplock branch:

- Reorganize locking in UVM and provide extra serialisation for pmap(9).
New lock order: [vmpage-owner-lock] -> pmap-lock.

- Simplify locking in some pmap(9) modules by removing P->V locking.

- Use lock object on vmobjlock (and thus vnode_t::v_interlock) to share
the locks amongst UVM objects where necessary (tmpfs, layerfs, unionfs).

- Rewrite and optimise x86 TLB shootdown code, make it simpler and cleaner.
Add TLBSTATS option for x86 to collect statistics about TLB shootdowns.

- Unify /dev/mem et al in MI code and provide required locking (removes
kernel-lock on some ports). Also, avoid cache-aliasing issues.

Thanks to Andrew Doran and Joerg Sonnenberger, as their initial patches
formed the core changes of this branch.

branches: 1.101.2;
Preliminary ARM11 MPCore support.

I have confirmed this commit doesn't affect existing evbarm kernels by
comparing binaries.

branches: 1.100.2;
Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.

Cleanup the armv7 changes. Add ARM_ARCH_7. Use CPU_CORTEX instead of
CPU_CORTEXA8 everywhere since there more types of Cortex than just the A8.
CPU_CORTEXA8 still exists but causes CPU_CORTEX to be defined.
Add CPU_CORTEXA9 as well. Use .arch armv7a to get us the isb/dsb
instructions.

Test booted to root device prompt on a Beagleboard.
All ARM kernels successfully test built.

PR port-arm/43299: Support added for igepv2/cortexa8/omap3530

Apply patch from PR, with build fixes. ok skrll, matt

branches: 1.97.2; 1.97.4;
Add write-through cache work-around for ARM11 as well as ARM9/ARM10. Analyzed
& tested on i.MX35 with help from Tsubai Masanari.

Adapt the arm32 fusu implementation for use on PROG26 configurations
and use it on acorn26.

Move arch/arm/arm32/fusu.S to arch/arm/arm/fusu.S in preparation for making
it usable on acorn26 as well.

Make the emulations, exec formats, coredump, NFS, and the NFS server
into modules. By and large this commit:

- shuffles header files and ifdefs
- splits code out where necessary to be modular
- adds module glue for each of the components
- adds/replaces hooks for things that can be installed at runtime

branches: 1.93.2; 1.93.8;
Add FA526 support (compile tested only)

Add CPU_CORTEXA8

branches: 1.91.2; 1.91.6;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.90.2; 1.90.4;
VFP support.

branches: 1.89.2; 1.89.6;
Add arm version of cpu_in_cksum. Based on previous in_cksum4 code.

In fact it's mostly the same code, with a different stub on it.

On a cats the regress/sys/net/in_cksum tests show that it takes around
50-60% of the time the C version takes. In some cases it takes as low as
20%.

Refactor in_cksum/in4_cksum/in6_cksum implementations:
- All three functions are included in the kernel by default.
They call a backend function cpu_in_cksum after possibly
computing the checksum of the pseudo header.
- cpu_in_cksum is the core to implement the one-complement sum.
The default implementation is moderate fast on most platforms
and provides a 32bit accumulator with 16bit addends for L32 platforms
and a 64bit accumulator with 32bit addends for L64 platforms.
It handles edge cases like very large mbuf chains (could happen with
native IPv6 in the future) and provides a good base for new native
implementations.
- Modify i386 and amd64 assembly to use the new interface.

This disables the MD implementations on !x86 until the conversion is
done. For Alpha, the portable version is faster.

Add MODULAR option. Include kernel linker stuff if MODULAR.

branches: 1.86.2; 1.86.8;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.85.6; 1.85.10; 1.85.12;
Remove leftover netns stuff.

merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.

branches: 1.83.2; 1.83.4; 1.83.8; 1.83.10;
Rewrite the ARM mutex implementation to be of the simple-mutex variety.
Because pre-v6 ARM lacks support for an atomic compare-and-swap, we
implement _lock_cas() as a restartable atomic squence that is checked
in the IRQ handler right before AST processing. (This is safe because,
for all practical purposes, there are no SMP pre-v6 ARM systems.)

This can serve as a model for other non-MP platforms that lack the
necessary atomic operations for mutexes (SuperH, for example).

Upshots of this change:
- kmutex_t is now down to 8 bytes on ARM; about as good as we can get.
- ARM2 systems don't have to trap and emulate SWP or SWPB for mutexes.

The acorn26 port is not updated by this commit to do the LOCK_CAS_CHECK.
That is left as an exercise for the port maintainer.

Reviewed and tested by Matt Thomas.

branches: 1.82.2;
Scott Allan in http://mail-index.netbsd.org/port-arm/2006/07/31/0000.html
Patch to add support for ARM9E

branches: 1.81.20; 1.81.24;
merge ktrace-lwp.

split compat_16 functions to their own file and make this compile again.

branches: 1.79.2;
The first step to support Intel PXA270.

kernel config option CPU_XSCALE_PXA2X0 is now obsoleted by
CPU_XSCALE_PXA250 and CPU_XSCALE_PXA270. If both of them are defined,
CPU is determined run-time.

Very basic support for the ARM1136.

This code takes no advantage of any 'new' features provided by
architecture 6 devices (such as physically tagged caches or new
MMU features), and basically runs the chip in a 'legacy v5' mode.

add an option to force ARM9 dcache to write-through mode.

Add "options ARM32_DISABLE_ALIGNMENT_FAULTS" to forcibly disable
alignment fault checking if necessary.

This option gets the acorn32 port working again.

XXX: Richard Earnshaw suggested enabling alignment faults for
XXX: userland only on acorn32. Need to investigate this.

Add a defflag for __BUS_SPACE_HAS_STREAM_METHODS, and add the
appropriate glue in bus.h, contingent on the option being defined.

This allows stream methods to be available on a port-by-port basis.

Hand-optimised in_cksum/in4_cksum for ARM and XSCALE.
Contributed by Wasabi Systems, with input from Chris Gilbert,
Richard Earnshaw and David Laight.

Add build-system support for ARM10.

branches: 1.72.2;
support IXP425 Intel Network Processor
running on BigEndian

Move the new pmap from arm32/pmap_new.c to arm32/pmap.c, fully replacing
the old.

ARM32_PMAP_NEEDS_PTE_SYNC no longer exists.

Add arm32 machine-specific remote kgdb support. Largely
from PR port-arm/15530 by bsh@, but with some updates from
me, including a fresh arm32/kgdb_machdep.c--ported from pc532.

Defflag XSCALE_CACHE_READ_WRITE_ALLOCATE and XSCALE_NO_COALESCE_WRITES.

Add the generic arm32 bits of the new pmap, contributed by Wasabi Systems.

Some features of the new pmap are:

- It allows L1 descriptor tables to be shared efficiently between
multiple processes. A typical "maxusers 32" kernel, where NPROC is set
to 532, requires 35 L1s. A "maxusers 2" kernel runs quite happily
with just 4 L1s. This completely solves the problem of running out
of contiguous physical memory for allocating new L1s at runtime on a
busy system.

- Much improved cache/TLB management "smarts". This change ripples
out to encompass the low-level context switch code, which is also
much smarter about when to flush the cache/TLB, and when not to.

- Faster allocation of L2 page tables and associated metadata thanks,
in part, to the pool_cache enhancements recently contributed to
NetBSD by Wasabi Systems.

- Faster VM space teardown due to accurate referenced tracking of L2
page tables.

- Better/faster cache-alias tracking.

The new pmap is enabled by adding options ARM32_PMAP_NEW to the kernel
config file, and making the necessary changes to the port-specific
initarm() function. Several ports have already been converted and will
be committed shortly.

put options XSCALE_CACHE_WRITE_THROUGH into opt_cpuoptions.h.
add XSCALE_CACHE_WRITE_BACK.

Clean up evbarm interrupt support a little:
* Define an ARM_INTR_IMPL option, which specifies a header file
describing the interrupt implementation for the platform. Use
this instead of the list of EVBARM_BOARDTYPE checks.
* Make the s3c2xx0 interrupt dispatch code a bit more generic, and move
it to a generic location so that other platforms can use it.

This eliminates all uses of the EVBARM_BOARDTYPE stuff, so delete it.

make atomic_{set,clear}_bit() inline for arm32 ports, and
add <machine/atomic.h> for them.

branches: 1.63.2;
Move the arm32 copystr.S from arch/arm/arm32 to arch/arm/arm and add support
for 26-bit modes (basically saving R14 when we might get a page fault).
Use it on all ARM architectures now.

New, improved version of copyin(), copyout(), and kcopy() by Allen Briggs.
This version works on both 26-bit and 32-bit machines. For large copies,
it's up to three times as fast as the old arm32 version and five times as
fast as the old arm26 version. For small copies it seems to be even faster
(getrusage() is apparently over ten times faster on an ARM610).

Hooray for Allen!

add support for ixp12x0

branches: 1.60.2; 1.60.4;
Add correct use of cpu types for SA1100 and SA1110.

Add the CPU_XSCALE_PXA2X0 option. From Hiroyuki Bessho, PR 16617.

Add some generic bus_space ops, which are pulled in by the
"bus_space_generic" configuration attribute.

Centralize ARM CPU configuration information by adding a new header
file, <arm/cpuconf.h>, which pulls in "opt_cputypes.h" and then defines
the following:
* CPU_NTYPES -- now many CPU types are configured into the kernel. What
you really want to know is "== 1" or "> 1".
* Defines ARM_ARCH_2, ARM_ARCH_3, ARM_ARCH_4, ARM_ARCH_5, depending
on which ARM architecture versions are configured (based on CPU_*
options). Also defines ARM_NARCH to determins how many architecture
versions are configured.
* Defines ARM_MMU_MEMC, ARM_MMU_GENERIC, ARM_MMU_XSCALE depending on
which classes of ARM MMUs are configured into the kernel, and ARM_NMMUS
to determine how many MMU classes are configured.

Remove the needless inclusion of "opt_cputypes.h" in several places.
Convert remaining users to <arm/cpuconf.h>.

Restructure a few things in order to support other XScale core
I/O processors:
* The i80200 and the i80321 have the same CPU ID, so split the
CPU_XSCALE option into CPU_XSCALE_80200 and CPU_XSCALE_80321
options, and don't let them both be defined at the same time.
XXX May want to revisit this in the future.
* Split some registers common between the i80200 and i80321 into
<arm/xscale/xscalereg.h>.
* Rename a few existing functions.

arm26->acorn26 transition.

Add a sleep routine for the SA-11x0.

Two changes for XScale:
1) Add defparam XSCALE_CCLKCFG to define a parameter for the
CCLKCFG register. Default it to '9' on the IQ80310.
2) Add a sleep call to the xscale CPU function vector (replacing
the nullop) which should drop the CPU into "idle" mode when
cpu_switch finds nothing on the run queues.

Separate out syscall() out into three parts:
swi_handler() does stuff that all SWIs will need, then calls
curproc->p_emul->e_syscall.
syscall() handles native NetBSD system calls.
linux_syscall() handles Linux system calls.

Crude first cut at ARMLinux binary compatibility. Successfully runs
"/emul/linux/bin/echo hello, world", dynamically linked.

Combined syscall handler for all ARM ports. This is basically the arm32
version, made readable and compatible with arm26. In addition, this adds
support for NetBSD/arm's newly allocated SWI range.

On arm26, vectors.S needs to be at the start of the kernel text, so that it's
on a page boundary and can be mapped straight into zero page. This means it
has to be in MD_SFILES on arm26, and not in SFILES.

This probably leaves kernel_text in the wrong place, but it at least leaves the system bootable.

Merge ast() and userret() between arm32 and arm26. The implementation used
is the arm32 one.

* Share a common vector page between arm26 and arm32.
* Use a common set of exception handlers for all arm32 platforms.
* New FIQ framework based on discussions with Ben Harris, shared
between arm26 and arm32.

- convert usage of "defopt" to "defflag" where the relevant option does
not support a value (e.g., it's to be used as "options FOO" instead of
"options FOO=xxx"). options that take a value were converted to
defparam recently.
- minor whitespace & formatting cleanups

Move the interrupt-related file declarations into port-specific
config descriptions so that each port choose whether or not to
use it.

Make the ARM, Ltd. floating point emulator work w/ ELF.

Move the ARM, Ltd. floating point emulator to arch/arm.

Add 26-bit and 32-bit types.h files, which indicate the programming
model in use for a given platform (__PROG26 vs __PROG32), then pulls
in <arm/types.h>. Change each ARM port to pull in <arm/arm26/types.h>
or <arm/arm32/types.h> as appropriate. Change all references to PROG26
and PROG32 to __PROG26 and __PROG32. Eliminate the opt_progmode.h
header file.

cleanup:
options SPACE TAB
makeoptions TAB
psuedo-device TAB
remove trailing whitespace
replace multiple spaces -> tabs
options "FOO" -> options FOO
options "FOO=bar" -> options FOO=bar
options "FOO=\"bar\"" -> options FOO="\"bar\""

branches: 1.40.2;
Split all the model/version-specific cpufuncs into separate files
corresponding to the model/version.

branches: 1.39.2;
Add CPU_ARM9 to opt_cputypes.h

Don't compile SPL/INTR stuff if NEWINTR is defined.

Share procfs_machdep.c across arm.

Add a CPU_XSCALE defopt (for eventual support).

Move the generic arm32 files into arm/arm32 from arm32/arm32, tested kernel builds on cats and riscpc.

Purge CPU_ARM7500. Thanks to Reinoud's work, it's no longer needed.

branches: 1.33.2;
Initial copy of SA11x0 support from hpcarm.

Merge arm32/dev/bus_space_notimpl.S and hpcarm/hpcarm/bus_space_notimpl.S
into arm/arm/bus_space_notimpl.S. They were identical anyway.

This file has no excuse for being in assembler, but I'll leave that for another
day.

Replace arm/arm32/db_trace.c and arm26/arm26/db_trace.c with a unified version
in arm/arm. This version is based on the arm26 version, and includes dumping
the contents of stack frames, with automatic determination of the save code
pointer offset.

Add support for ARM7TDMI, as provided in a patch from John Fremlin to port-arm32.

Shouldn't effect any currently in tree ports.

Move blockio.S from sys/arch/arm32/arm32 to sys/arch/arm/arm, since I want to
start using it on arm26.

hpcarm gets to keep its own version, since it's not identical and I haven't
got an hpcarm box to test.

Create an asm based version of in4_cksum based on the sparc version.

Also don't compute psuedo header for nxt == 0

strstr() is no longer used in the kernel. G/C it.

Move get_bootconf_option() into a new file, sys/arch/arm/arm/bootconfig.c,
since it's in no way machine-dependent. It's not really ARM-specific either,
but I don't think it's useful enough to be made part of the MI kernel.

Move "defopt PMAP_DEBUG" into files.arm, since it's used by code in arch/arm.

Move cpufunc stuff from arm32/arm32 to arm/arm. The only change involved is
to add recognition of the SA-1100 and SA-1110 for compatibility with hpcarm
(which is now using this code as well).

Split cpu from mainbus so that cpu can attached to other buses (like ofbus).

Move references to arm/arm/disksubr*.c from files.arm to
files.{arm26,arm32,dnard}.

"needs-flag" for cpu is no longer needed.

Use the same undefined-instuction handler on both arm26 and arm32. The handler
is derived mostly from the arm32 version, but with a check for an obscure ARM2
bug thrown in.

arm26 fpu and cpu drivers use the new interface for catching undefined
instructions.

Move arm32/arm32/ast.c to arm/arm32/ast.c

Move undefined.c from sys/arch/{arm32/arm32,hpcarm/hpcarm} to sys/arch/arm/arm
in preparation for making it usable on arm26 as well.

branches: 1.17.2;
Merge setregs() from sys/arch/arm32/arm32/machdep.c,
sys/arch/hpcarm/hpcarm/machdep.c and sys/arch/arm26/arm26/vm_machdep.c
into sys/arch/arm/arm/arm_machdep.c.

Make compat_13_sys_sigreturn() work on arm26, and move it from
arch/arm/arm32/compat_13_machdep.c to arch/arm/arm/compat_13_machdep.c.

Move compat_13_machdep.c, strstr.c, copystr.S, bcopyinout.S, and
bcopy_page.S to arm/arm32 and remove port-local copies.

disksubr*.c are now shared. Start moving files from ../../arm32/arm32

Move "options ARMFPE" to files.arm, so generic ARM files can use it.

Add PROG32 and PROG26 options.

These are intended to indicate what size of program space is in use, and hence
how to get at the PSR bits. They're currently set automatically by the CPU
type options.

Allow "cpu" to have children. In the long term, this may be the best way to
handle co-processors. In the short term, it's a necessary hack to get arm26
kernels to configure.

Moved the mainbus files to the arm/conf/file.arm from the arm32 and the
hpcarm/conf/files.hpcarm

Big patch for merging common include files of the new hpcarm tree and the old arm32
tree into the new arm substree. All moved files are relinked with a stub that included
the file from the new location; this might be done better later.

Move cpu_coredump() from arm32/arm32/vm_machdep.c to arm/arm/vm_machdep_arm.c.
Also ANSIfy it and use it on arm26.

Move sendsig() and sys___sigreturn14() from arm26/arm26/vm_machdep.c and
arm32/arm32/machdep.c into arm/arm/sig_machdep.c, merging and ANSIfying in
the process.

The code is based on the arm32 version, so I don't think anything should break
there.

branches: 1.6.2;
Shared ARM ptrace(2) implementation. Mostly the same as the arm32
version, but with some #ifdefs for arm26.

Also, don't define PT_STEP, since we don't implement it. This should
reduce code size a little.

Separate out sigcode into its own file, since it's shared by arm26 and arm32.

Move db_disasm.c into sys/arch/arm/arm. Use arm26 version, since it should
generate smaller compiled code.

Move the generic ARM disassembler from arm32/arm32 to arm/arm.

Start merging actual code in arm32 and arm26:
arm32/arm32/in_cksum_arm32.c -> arm/arm/in_cksum_arm.c

Also move specification of other checksum stuff to files.arm, even though we
use the MI code for that.

Empty file to keep config happy.

MI PMAP EFI_RUNTIME support

Update to support EFI runtime outside the kernel virtual address space
by creating an EFI RT pmap that can be activated / deactivated when
required.

Adds support for EFI RT to ARM_MMU_EXTENDED (ASID) 32-bit Arm machines.

On Arm64 the usage of pmapboot_enter is reduced and the mappings are
created much later in the boot process -- now in cpu_startup_hook.
Backward compatiblity for KVA mapped RT from old bootaa64.efi is
maintained.

Adding support to other platforms should be easier as a result.

Arm: Add support for SMC Calling Convention

Arm DEN0028 defines a calling mechanism used with Secure Monitor Call (SMC)
and Hypervisor Call (HVC) instructions. To discover SMCCC, we must:

1) Find the PSCI conduit (either via ACPI FADT, or Device Tree)
2) Use PSCI_VERSION to determine whether PSCI_FEATURES is supported
3) Call PSCI_FEATURES with SMCCC_VERSION to determine the implementation
version.

make process_machdep.c included always since it provides register i/o used by
sys_process_getlwpstatus.c which is always included.

harmonize process_machdep.c inclusion.

Collapse all CPU_CORTEXA<n> options into CPU_CORTEX and do runtime
detection instead of ifdefs where required.

Add support for Privileged Access Never (ARMv8.1-PAN).

PAN provides the same functionality as SMAP on x86: it forbids kernel
access to userland pages when PSTATE.PAN=1, and allows such accesses when
PSTATE.PAN=0.

We clear SCTLR_SPAN, to guarantee that PAN=1 each time the kernel is
entered. We catch PAN faults and panic right away without further
processing. In copyin, copyout, etc, we temporarily authorize access to
userland pages.

PAN is a very useful exploit mitigation. Reviewed by ryo@, thanks. Tested
on Qemu. Enabled by default.

Enable ChaCha NEON code on armv7 too.

The 4-blocks-at-a-time assembly helper is disabled for now; adapting
it to armv7 is going to be a little annoying with only 16 128-bit
vector registers.

(Should also do a fifth block in the integer registers for 320 bytes
at a time.)

Fix outdated comment.

New permutation-based AES implementation using ARM NEON.

Also derived from Mike Hamburg's public-domain vpaes code.

PMAP_DEBUG has been deleted on arm

Add KASAN-DMA support on aarch64, same as amd64. Discussed with skrll@.

Add support for Branch Target Identification (BTI).

On the executable pages that have the GP (Guarded Page) bit, the semantic
of the "br" and "blr" instructions is changed: the CPU expects the first
instruction of the jump/call target to be "bti", and faults if it isn't.

We add the GP bit on the kernel .text pages (and incidentally the .rodata
pages, but we don't care). The compiler adds a "bti c" instruction at the
beginning of each C function. We modify the ENTRY() macros to manually add
"bti c" in the asm functions.

cpuswitch.S needs a specific change: with "br x27" the CPU expects "bti j",
which is bad because the functions begin with "bti c"; switch to "br x16",
for the CPU to accept "bti c".

BTI helps defend against JOP/COP. Tested on Qemu.

Add support for Pointer Authentication (PAC).

We use the "pac-ret" option, to sign the return instruction pointer on
function entry, and authenticate it on function exit. This acts as a
mitigation against ROP.

The authentication uses a per-lwp (secret) I-A key stored in the 128bit
APIAKey register and part of the lwp context. During lwp creation, the
kernel generates a random key, and during context switches, it installs
the key of the target lwp on the CPU.

Userland cannot read the APIAKey register directly. However, it can sign
its pointers with it, because the register is architecturally shared
between userland and the kernel. Although part of the CPU design, it is
a bit of an undesired behavior, because it allows to forge valid kernel
pointers from userland. To avoid that, we don't share the key with
userland, and rather switch it in EL0<->EL1 transitions. This means that
when userland executes, a different key is loaded in APIAKey than the one
the kernel uses. For now the userland key is a fixed 128bit zero value.

The DDB stack unwinder is changed to strip the authentication code from
the pointers in lr.

Two problems are known:

* Currently the idlelwps' keys are not really secret. This is because
the RNG is not yet available when we spawn these lwps. Not overly
important, but would be nice to fix with UEFI RNG.
* The key switching in EL0<->EL1 transitions is not the most optimized
code on the planet. Instead of checking aarch64_pac_enabled, it would
be better to hot-patch the code at boot time, but there currently is
no hot-patch support on aarch64.

Tested on Qemu.

branches: 1.153.4;
Various updates and improvements to cpu start up on arm/aarch64

- start sharing more code around the AP startup messaging.
- call arm_cpu_topology_set early so that ci_core_id is available for
drivers, e.g. bcm2835_intr.c
- both arm and aarch64 now have
- a static cpu_info_store array
- the same arm_cpu_{hatched,mbox}

Sort a bit

Trailing whitespace

port the arm64 cpu topology setup for big.little to arm.

rename arm64 cpu_do_topology() to arm_cpu_do_topology() and
call it from both arm cpu_attach().

replace both aarch64_set_topology() inline code in arm
cpu_attach() with new arm_cpu_do_topology(), which is called
by the arm64 locore as well (possibly not needed, which would
allow it to become static.)

not yet tested on a real big.little armv7 system. tested
on rockpro64 and pinebook pro.

branches: 1.149.2;
Move all non-emulation-specific coredump code into the coredump module,
and remove all #ifdef COREDUMP conditional compilation. Now, the
coredump module is completely separated from the emulation modules, and
they can all be independently loaded and unloaded.

Welcome to 9.99.18 !

Merge the [pgoyette-compat] branch

Split armv7/armv8 tprof backend config logic from the fdt bus glue.

Add support for EFI runtime services on aarch64.

Provide generic start code that assumes the MMU is off and caches are
disabled as per the linux booting protocol for ARMv6 and ARMv7 boards.
u-boot image type should be changed to 'linux' for correct behaviour.

The new start code builds a minimal "bootstrap" L1PT with cached access
disabled and uses the same table for all processors. AP startup is
performed in less steps and more code is written in C.

The bootstrap tables and stack are placed into an (orphaned) section
"_init_memory" which is given to uvm when it is no longer used.

Various kernels have been converted to use this code and tested. Some
boards were provided by TNF. Thanks!

The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS
kernels. The GENERIC kernel will also work on RPI2 using u-boot.

Thanks to martin@ and aymeric@ for testing on parallella and nanosoc
respectively

Whitespace

Centralise defparam CONSADDR, CONSPEED, CONMODE and CONADDR into
opt_console.h and adjust.

Whitespace

remove reference to CPU_ARMV2, suggested by jmcneill@

Retire CPU_ARM2, CPU_ARM250 and CPU_ARM3, they are all leftovers of
acorn26.

ok jmcneill@ skrll@

branches: 1.139.2;
Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

branches: 1.138.2;
Remove port-acorn26

OK core@

G/C ARM32_NEW_VM_LAYOUT

Add CPU_CORTEXA35

defflag CPU_CORTEXA53

Add __HAVE_GENERIC_CPU_INITCLOCKS option. If set, don't export
cpu_initclocks from device drivers as common code (in this case FDT) will
provide its own copy.

Add support for ARM Power State Coordination Interface (PSCI).

branches: 1.132.2;
Recognize Cortex-A57 FPU, GIC, and Generic Timer.

Support pmap_pv_track and friends

According to the Cortex-A5 TRM, the CBAR register is not implemented and
always reads as 0x00000000. Add ARM_CBAR option to set this in kernel
config.

Add CPU_CORTEXA17

branches: 1.128.2;
Add option ARM_HAS_LPAE

branches: 1.127.2;
Support (untested) SHEEVA_L2_CACHE and SHEEVA_L2_CACHE_WT options.
Move prototypes out to <arm/cpufunc.h> to their own file.
Add sdcache routines to cpufunc_asm_sheeva.S
Add code sheeve_setup to init the sdcache and sdcache info.

branches: 1.126.2;
Make the ARM pmap use ASIDs, split TTBRs, and MP safe. This only happens for
ARMv6 or later CPUs. This means that on context switch that the TLBs and
caches no longer to cleaned/flushed. Also, eXecute Never (XN) protection has
been added so non-exec pages can not be run. Change the page size for ARMv6+
to be 8KB while allows a L1PT to be a normal page. This means that the L1PT
is not special. Use the XN support to only sync pages that are executed from.

defflag VERBOSE_INIT_ARM

cpu_cortex doesn't need the arm11 cpufuncs any more

CPU_ARMV[67] imply ARM32_DISABLE_ALIGNMENT_FAULTS
Make it explicit.

Nuke atomic.S since we have MI defined atomic ops

Rework to have CPU_PREARMV6, CPU_ARMV6, as well as CPU_ARMV7

branches: 1.120.2;
File VBAR option

Add a ARM_HAS_VBAR option which forces the use of the VBAR register. This
allows much code to deal with vector_page mappings to be eliminated. On a
BEAGLEBONE kernel, this saves 8KB of text and instructions that never have
to be executed. (The PJ4B has VBAR but doesn't implement the security
extensions it is part of so a method was needed to allow it use VBAR with
relying on the default test for the security extensions.)

Add CPU_ARMV7 and make CPU_PJ4B and CPU_CORTEX instantiate it.

Make PJ4B support code compilable.

Obtained from Marvell, Semihalf.

Add BUSDMA_COUNTERS option

Disable bzero_page_vfp and bcopy_page_vfp since it really isn't any faster
than memcpy.

Add code to use VFP(or Neon) instructions to zero or copy a page via
pmap_zero_page and pmap_copy_page. (Not hooked into vfp_init yet).
Requires FPU_VFP

ARMFPE hasn't compiled since NetBSD 4. Remove it.
Complete support for FPU_VFP.
fpregs now contains vfpreg.
XXX vfpreg only has space for 16 64-bit FP registers though VFPv3 and later
have 32 64-bit FP registers.

Add a PMAP_NEEDS_ALLOC_POOLPAGE / PMAP_ALLOC_POOLPAGE hook so systems can
allocate pool pages from a specific VM freelist.

add _ARM32_NEED_BUS_DMA_BOUNCE to opt_arm_bus_space.h (It's not really a
bus_space option but it's close enough).

branches: 1.110.2;
Add core locator to mainbus. Add support for attaching multiple CPUs

Rename ARM options PROCESS_ID_IS_CUR{CPU,LWP} to TPIDRPRW_IS_CUR{CPU,LWP}
since TPIDRPRW is the cp15 register name.
Initialize it early in start along with CI_ARM_CPUID.
Remove other initializations.
We alays have ci_curlwp.
Enable TIPRPRW_IS_CURCPU in std.beagle.
[tested on a beaglboard (cortex-a8)]

Rework VFP support to use PCU.
Add emulation of instruction which save/restore the VFP FPSCR.
Add a sysarch hook to VFP FPSCR manipulation.

[The emulation will be used by libc to store/fetch exception modes and
rounding mode on a per-thread basis.]

COMPAT_NETBSD32 support for ARM. Which is strange since ARM is already
32-bits. But the newer ARM ABI AAPCS changes the alignment of 64-bit
fields so structures need to copied in and out to deal with the alignment
change. This is a kludge but makes debugging of AAPCS support much easier.

Add support for the ARM1176JZS

Add intrbase locator to mainbus.

Begin support for Cortex A5, A7, A15 and expand A8 and A9 definitions.
Instead of testing all possible CPUids for a cortex, we know what range
a cortex will be so mask out the insignificant parts and do a single test.

branches: 1.103.2;
Require arm3_cache_flush for ARM2/ARM250.

branches: 1.102.2; 1.102.6;
Welcome to 5.99.53! Merge rmind-uvmplock branch:

- Reorganize locking in UVM and provide extra serialisation for pmap(9).
New lock order: [vmpage-owner-lock] -> pmap-lock.

- Simplify locking in some pmap(9) modules by removing P->V locking.

- Use lock object on vmobjlock (and thus vnode_t::v_interlock) to share
the locks amongst UVM objects where necessary (tmpfs, layerfs, unionfs).

- Rewrite and optimise x86 TLB shootdown code, make it simpler and cleaner.
Add TLBSTATS option for x86 to collect statistics about TLB shootdowns.

- Unify /dev/mem et al in MI code and provide required locking (removes
kernel-lock on some ports). Also, avoid cache-aliasing issues.

Thanks to Andrew Doran and Joerg Sonnenberger, as their initial patches
formed the core changes of this branch.

branches: 1.101.2;
Preliminary ARM11 MPCore support.

I have confirmed this commit doesn't affect existing evbarm kernels by
comparing binaries.

branches: 1.100.2;
Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.

Cleanup the armv7 changes. Add ARM_ARCH_7. Use CPU_CORTEX instead of
CPU_CORTEXA8 everywhere since there more types of Cortex than just the A8.
CPU_CORTEXA8 still exists but causes CPU_CORTEX to be defined.
Add CPU_CORTEXA9 as well. Use .arch armv7a to get us the isb/dsb
instructions.

Test booted to root device prompt on a Beagleboard.
All ARM kernels successfully test built.

PR port-arm/43299: Support added for igepv2/cortexa8/omap3530

Apply patch from PR, with build fixes. ok skrll, matt

branches: 1.97.2; 1.97.4;
Add write-through cache work-around for ARM11 as well as ARM9/ARM10. Analyzed
& tested on i.MX35 with help from Tsubai Masanari.

Adapt the arm32 fusu implementation for use on PROG26 configurations
and use it on acorn26.

Move arch/arm/arm32/fusu.S to arch/arm/arm/fusu.S in preparation for making
it usable on acorn26 as well.

Make the emulations, exec formats, coredump, NFS, and the NFS server
into modules. By and large this commit:

- shuffles header files and ifdefs
- splits code out where necessary to be modular
- adds module glue for each of the components
- adds/replaces hooks for things that can be installed at runtime

branches: 1.93.2; 1.93.8;
Add FA526 support (compile tested only)

Add CPU_CORTEXA8

branches: 1.91.2; 1.91.6;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.90.2; 1.90.4;
VFP support.

branches: 1.89.2; 1.89.6;
Add arm version of cpu_in_cksum. Based on previous in_cksum4 code.

In fact it's mostly the same code, with a different stub on it.

On a cats the regress/sys/net/in_cksum tests show that it takes around
50-60% of the time the C version takes. In some cases it takes as low as
20%.

Refactor in_cksum/in4_cksum/in6_cksum implementations:
- All three functions are included in the kernel by default.
They call a backend function cpu_in_cksum after possibly
computing the checksum of the pseudo header.
- cpu_in_cksum is the core to implement the one-complement sum.
The default implementation is moderate fast on most platforms
and provides a 32bit accumulator with 16bit addends for L32 platforms
and a 64bit accumulator with 32bit addends for L64 platforms.
It handles edge cases like very large mbuf chains (could happen with
native IPv6 in the future) and provides a good base for new native
implementations.
- Modify i386 and amd64 assembly to use the new interface.

This disables the MD implementations on !x86 until the conversion is
done. For Alpha, the portable version is faster.

Add MODULAR option. Include kernel linker stuff if MODULAR.

branches: 1.86.2; 1.86.8;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

branches: 1.85.6; 1.85.10; 1.85.12;
Remove leftover netns stuff.

merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.

branches: 1.83.2; 1.83.4; 1.83.8; 1.83.10;
Rewrite the ARM mutex implementation to be of the simple-mutex variety.
Because pre-v6 ARM lacks support for an atomic compare-and-swap, we
implement _lock_cas() as a restartable atomic squence that is checked
in the IRQ handler right before AST processing. (This is safe because,
for all practical purposes, there are no SMP pre-v6 ARM systems.)

This can serve as a model for other non-MP platforms that lack the
necessary atomic operations for mutexes (SuperH, for example).

Upshots of this change:
- kmutex_t is now down to 8 bytes on ARM; about as good as we can get.
- ARM2 systems don't have to trap and emulate SWP or SWPB for mutexes.

The acorn26 port is not updated by this commit to do the LOCK_CAS_CHECK.
That is left as an exercise for the port maintainer.

Reviewed and tested by Matt Thomas.

branches: 1.82.2;
Scott Allan in http://mail-index.netbsd.org/port-arm/2006/07/31/0000.html
Patch to add support for ARM9E

branches: 1.81.20; 1.81.24;
merge ktrace-lwp.

split compat_16 functions to their own file and make this compile again.

branches: 1.79.2;
The first step to support Intel PXA270.

kernel config option CPU_XSCALE_PXA2X0 is now obsoleted by
CPU_XSCALE_PXA250 and CPU_XSCALE_PXA270. If both of them are defined,
CPU is determined run-time.

Very basic support for the ARM1136.

This code takes no advantage of any 'new' features provided by
architecture 6 devices (such as physically tagged caches or new
MMU features), and basically runs the chip in a 'legacy v5' mode.

add an option to force ARM9 dcache to write-through mode.

Add "options ARM32_DISABLE_ALIGNMENT_FAULTS" to forcibly disable
alignment fault checking if necessary.

This option gets the acorn32 port working again.

XXX: Richard Earnshaw suggested enabling alignment faults for
XXX: userland only on acorn32. Need to investigate this.

Add a defflag for __BUS_SPACE_HAS_STREAM_METHODS, and add the
appropriate glue in bus.h, contingent on the option being defined.

This allows stream methods to be available on a port-by-port basis.

Hand-optimised in_cksum/in4_cksum for ARM and XSCALE.
Contributed by Wasabi Systems, with input from Chris Gilbert,
Richard Earnshaw and David Laight.

Add build-system support for ARM10.

branches: 1.72.2;
support IXP425 Intel Network Processor
running on BigEndian

Move the new pmap from arm32/pmap_new.c to arm32/pmap.c, fully replacing
the old.

ARM32_PMAP_NEEDS_PTE_SYNC no longer exists.

Add arm32 machine-specific remote kgdb support. Largely
from PR port-arm/15530 by bsh@, but with some updates from
me, including a fresh arm32/kgdb_machdep.c--ported from pc532.

Defflag XSCALE_CACHE_READ_WRITE_ALLOCATE and XSCALE_NO_COALESCE_WRITES.

Add the generic arm32 bits of the new pmap, contributed by Wasabi Systems.

Some features of the new pmap are:

- It allows L1 descriptor tables to be shared efficiently between
multiple processes. A typical "maxusers 32" kernel, where NPROC is set
to 532, requires 35 L1s. A "maxusers 2" kernel runs quite happily
with just 4 L1s. This completely solves the problem of running out
of contiguous physical memory for allocating new L1s at runtime on a
busy system.

- Much improved cache/TLB management "smarts". This change ripples
out to encompass the low-level context switch code, which is also
much smarter about when to flush the cache/TLB, and when not to.

- Faster allocation of L2 page tables and associated metadata thanks,
in part, to the pool_cache enhancements recently contributed to
NetBSD by Wasabi Systems.

- Faster VM space teardown due to accurate referenced tracking of L2
page tables.

- Better/faster cache-alias tracking.

The new pmap is enabled by adding options ARM32_PMAP_NEW to the kernel
config file, and making the necessary changes to the port-specific
initarm() function. Several ports have already been converted and will
be committed shortly.

put options XSCALE_CACHE_WRITE_THROUGH into opt_cpuoptions.h.
add XSCALE_CACHE_WRITE_BACK.

Clean up evbarm interrupt support a little:
* Define an ARM_INTR_IMPL option, which specifies a header file
describing the interrupt implementation for the platform. Use
this instead of the list of EVBARM_BOARDTYPE checks.
* Make the s3c2xx0 interrupt dispatch code a bit more generic, and move
it to a generic location so that other platforms can use it.

This eliminates all uses of the EVBARM_BOARDTYPE stuff, so delete it.

make atomic_{set,clear}_bit() inline for arm32 ports, and
add <machine/atomic.h> for them.

branches: 1.63.2;
Move the arm32 copystr.S from arch/arm/arm32 to arch/arm/arm and add support
for 26-bit modes (basically saving R14 when we might get a page fault).
Use it on all ARM architectures now.

New, improved version of copyin(), copyout(), and kcopy() by Allen Briggs.
This version works on both 26-bit and 32-bit machines. For large copies,
it's up to three times as fast as the old arm32 version and five times as
fast as the old arm26 version. For small copies it seems to be even faster
(getrusage() is apparently over ten times faster on an ARM610).

Hooray for Allen!

add support for ixp12x0

branches: 1.60.2; 1.60.4;
Add correct use of cpu types for SA1100 and SA1110.

Add the CPU_XSCALE_PXA2X0 option. From Hiroyuki Bessho, PR 16617.

Add some generic bus_space ops, which are pulled in by the
"bus_space_generic" configuration attribute.

Centralize ARM CPU configuration information by adding a new header
file, <arm/cpuconf.h>, which pulls in "opt_cputypes.h" and then defines
the following:
* CPU_NTYPES -- now many CPU types are configured into the kernel. What
you really want to know is "== 1" or "> 1".
* Defines ARM_ARCH_2, ARM_ARCH_3, ARM_ARCH_4, ARM_ARCH_5, depending
on which ARM architecture versions are configured (based on CPU_*
options). Also defines ARM_NARCH to determins how many architecture
versions are configured.
* Defines ARM_MMU_MEMC, ARM_MMU_GENERIC, ARM_MMU_XSCALE depending on
which classes of ARM MMUs are configured into the kernel, and ARM_NMMUS
to determine how many MMU classes are configured.

Remove the needless inclusion of "opt_cputypes.h" in several places.
Convert remaining users to <arm/cpuconf.h>.

Restructure a few things in order to support other XScale core
I/O processors:
* The i80200 and the i80321 have the same CPU ID, so split the
CPU_XSCALE option into CPU_XSCALE_80200 and CPU_XSCALE_80321
options, and don't let them both be defined at the same time.
XXX May want to revisit this in the future.
* Split some registers common between the i80200 and i80321 into
<arm/xscale/xscalereg.h>.
* Rename a few existing functions.

arm26->acorn26 transition.

Add a sleep routine for the SA-11x0.

Two changes for XScale:
1) Add defparam XSCALE_CCLKCFG to define a parameter for the
CCLKCFG register. Default it to '9' on the IQ80310.
2) Add a sleep call to the xscale CPU function vector (replacing
the nullop) which should drop the CPU into "idle" mode when
cpu_switch finds nothing on the run queues.

Separate out syscall() out into three parts:
swi_handler() does stuff that all SWIs will need, then calls
curproc->p_emul->e_syscall.
syscall() handles native NetBSD system calls.
linux_syscall() handles Linux system calls.

Crude first cut at ARMLinux binary compatibility. Successfully runs
"/emul/linux/bin/echo hello, world", dynamically linked.

Combined syscall handler for all ARM ports. This is basically the arm32
version, made readable and compatible with arm26. In addition, this adds
support for NetBSD/arm's newly allocated SWI range.

On arm26, vectors.S needs to be at the start of the kernel text, so that it's
on a page boundary and can be mapped straight into zero page. This means it
has to be in MD_SFILES on arm26, and not in SFILES.

This probably leaves kernel_text in the wrong place, but it at least leaves the system bootable.

Merge ast() and userret() between arm32 and arm26. The implementation used
is the arm32 one.

* Share a common vector page between arm26 and arm32.
* Use a common set of exception handlers for all arm32 platforms.
* New FIQ framework based on discussions with Ben Harris, shared
between arm26 and arm32.

- convert usage of "defopt" to "defflag" where the relevant option does
not support a value (e.g., it's to be used as "options FOO" instead of
"options FOO=xxx"). options that take a value were converted to
defparam recently.
- minor whitespace & formatting cleanups

Move the interrupt-related file declarations into port-specific
config descriptions so that each port choose whether or not to
use it.

Make the ARM, Ltd. floating point emulator work w/ ELF.

Move the ARM, Ltd. floating point emulator to arch/arm.

Add 26-bit and 32-bit types.h files, which indicate the programming
model in use for a given platform (__PROG26 vs __PROG32), then pulls
in <arm/types.h>. Change each ARM port to pull in <arm/arm26/types.h>
or <arm/arm32/types.h> as appropriate. Change all references to PROG26
and PROG32 to __PROG26 and __PROG32. Eliminate the opt_progmode.h
header file.

cleanup:
options SPACE TAB
makeoptions TAB
psuedo-device TAB
remove trailing whitespace
replace multiple spaces -> tabs
options "FOO" -> options FOO
options "FOO=bar" -> options FOO=bar
options "FOO=\"bar\"" -> options FOO="\"bar\""

branches: 1.40.2;
Split all the model/version-specific cpufuncs into separate files
corresponding to the model/version.

branches: 1.39.2;
Add CPU_ARM9 to opt_cputypes.h

Don't compile SPL/INTR stuff if NEWINTR is defined.

Share procfs_machdep.c across arm.

Add a CPU_XSCALE defopt (for eventual support).

Move the generic arm32 files into arm/arm32 from arm32/arm32, tested kernel builds on cats and riscpc.

Purge CPU_ARM7500. Thanks to Reinoud's work, it's no longer needed.

branches: 1.33.2;
Initial copy of SA11x0 support from hpcarm.

Merge arm32/dev/bus_space_notimpl.S and hpcarm/hpcarm/bus_space_notimpl.S
into arm/arm/bus_space_notimpl.S. They were identical anyway.

This file has no excuse for being in assembler, but I'll leave that for another
day.

Replace arm/arm32/db_trace.c and arm26/arm26/db_trace.c with a unified version
in arm/arm. This version is based on the arm26 version, and includes dumping
the contents of stack frames, with automatic determination of the save code
pointer offset.

Add support for ARM7TDMI, as provided in a patch from John Fremlin to port-arm32.

Shouldn't effect any currently in tree ports.

Move blockio.S from sys/arch/arm32/arm32 to sys/arch/arm/arm, since I want to
start using it on arm26.

hpcarm gets to keep its own version, since it's not identical and I haven't
got an hpcarm box to test.

Create an asm based version of in4_cksum based on the sparc version.

Also don't compute psuedo header for nxt == 0

strstr() is no longer used in the kernel. G/C it.

Move get_bootconf_option() into a new file, sys/arch/arm/arm/bootconfig.c,
since it's in no way machine-dependent. It's not really ARM-specific either,
but I don't think it's useful enough to be made part of the MI kernel.

Move "defopt PMAP_DEBUG" into files.arm, since it's used by code in arch/arm.

Move cpufunc stuff from arm32/arm32 to arm/arm. The only change involved is
to add recognition of the SA-1100 and SA-1110 for compatibility with hpcarm
(which is now using this code as well).

Split cpu from mainbus so that cpu can attached to other buses (like ofbus).

Move references to arm/arm/disksubr*.c from files.arm to
files.{arm26,arm32,dnard}.

"needs-flag" for cpu is no longer needed.

Use the same undefined-instuction handler on both arm26 and arm32. The handler
is derived mostly from the arm32 version, but with a check for an obscure ARM2
bug thrown in.

arm26 fpu and cpu drivers use the new interface for catching undefined
instructions.

Move arm32/arm32/ast.c to arm/arm32/ast.c

Move undefined.c from sys/arch/{arm32/arm32,hpcarm/hpcarm} to sys/arch/arm/arm
in preparation for making it usable on arm26 as well.

branches: 1.17.2;
Merge setregs() from sys/arch/arm32/arm32/machdep.c,
sys/arch/hpcarm/hpcarm/machdep.c and sys/arch/arm26/arm26/vm_machdep.c
into sys/arch/arm/arm/arm_machdep.c.

Make compat_13_sys_sigreturn() work on arm26, and move it from
arch/arm/arm32/compat_13_machdep.c to arch/arm/arm/compat_13_machdep.c.

Move compat_13_machdep.c, strstr.c, copystr.S, bcopyinout.S, and
bcopy_page.S to arm/arm32 and remove port-local copies.

disksubr*.c are now shared. Start moving files from ../../arm32/arm32

Move "options ARMFPE" to files.arm, so generic ARM files can use it.

Add PROG32 and PROG26 options.

These are intended to indicate what size of program space is in use, and hence
how to get at the PSR bits. They're currently set automatically by the CPU
type options.

Allow "cpu" to have children. In the long term, this may be the best way to
handle co-processors. In the short term, it's a necessary hack to get arm26
kernels to configure.

Moved the mainbus files to the arm/conf/file.arm from the arm32 and the
hpcarm/conf/files.hpcarm

Big patch for merging common include files of the new hpcarm tree and the old arm32
tree into the new arm substree. All moved files are relinked with a stub that included
the file from the new location; this might be done better later.

Move cpu_coredump() from arm32/arm32/vm_machdep.c to arm/arm/vm_machdep_arm.c.
Also ANSIfy it and use it on arm26.

Move sendsig() and sys___sigreturn14() from arm26/arm26/vm_machdep.c and
arm32/arm32/machdep.c into arm/arm/sig_machdep.c, merging and ANSIfying in
the process.

The code is based on the arm32 version, so I don't think anything should break
there.

branches: 1.6.2;
Shared ARM ptrace(2) implementation. Mostly the same as the arm32
version, but with some #ifdefs for arm26.

Also, don't define PT_STEP, since we don't implement it. This should
reduce code size a little.

Separate out sigcode into its own file, since it's shared by arm26 and arm32.

Move db_disasm.c into sys/arch/arm/arm. Use arm26 version, since it should
generate smaller compiled code.

Move the generic ARM disassembler from arm32/arm32 to arm/arm.

Start merging actual code in arm32 and arm26:
arm32/arm32/in_cksum_arm32.c -> arm/arm/in_cksum_arm.c

Also move specification of other checksum stuff to files.arm, even though we
use the MI code for that.

Empty file to keep config happy.

Update to support EFI runtime outside the kernel virtual address space
by creating an EFI RT pmap that can be activated / deactivated when
required.

Adds support for EFI RT to ARM_MMU_EXTENDED (ASID) 32-bit Arm machines.

On Arm64 the usage of pmapboot_enter is reduced and the mappings are
created much later in the boot process -- now in cpu_startup_hook.
Backward compatiblity for KVA mapped RT from old bootaa64.efi is
maintained.

Adding support to other platforms should be easier as a result.

Arm: Add support for SMC Calling Convention

Arm DEN0028 defines a calling mechanism used with Secure Monitor Call (SMC)
and Hypervisor Call (HVC) instructions. To discover SMCCC, we must:

1) Find the PSCI conduit (either via ACPI FADT, or Device Tree)
2) Use PSCI_VERSION to determine whether PSCI_FEATURES is supported
3) Call PSCI_FEATURES with SMCCC_VERSION to determine the implementation
version.

make process_machdep.c included always since it provides register i/o used by
sys_process_getlwpstatus.c which is always included.

harmonize process_machdep.c inclusion.

Collapse all CPU_CORTEXA<n> options into CPU_CORTEX and do runtime
detection instead of ifdefs where required.

Add support for Privileged Access Never (ARMv8.1-PAN).

PAN provides the same functionality as SMAP on x86: it forbids kernel
access to userland pages when PSTATE.PAN=1, and allows such accesses when
PSTATE.PAN=0.

We clear SCTLR_SPAN, to guarantee that PAN=1 each time the kernel is
entered. We catch PAN faults and panic right away without further
processing. In copyin, copyout, etc, we temporarily authorize access to
userland pages.

PAN is a very useful exploit mitigation. Reviewed by ryo@, thanks. Tested
on Qemu. Enabled by default.

Enable ChaCha NEON code on armv7 too.

The 4-blocks-at-a-time assembly helper is disabled for now; adapting
it to armv7 is going to be a little annoying with only 16 128-bit
vector registers.

(Should also do a fifth block in the integer registers for 320 bytes
at a time.)

Fix outdated comment.

New permutation-based AES implementation using ARM NEON.

Also derived from Mike Hamburg's public-domain vpaes code.

PMAP_DEBUG has been deleted on arm

Add KASAN-DMA support on aarch64, same as amd64. Discussed with skrll@.

Add support for Branch Target Identification (BTI).

On the executable pages that have the GP (Guarded Page) bit, the semantic
of the "br" and "blr" instructions is changed: the CPU expects the first
instruction of the jump/call target to be "bti", and faults if it isn't.

We add the GP bit on the kernel .text pages (and incidentally the .rodata
pages, but we don't care). The compiler adds a "bti c" instruction at the
beginning of each C function. We modify the ENTRY() macros to manually add
"bti c" in the asm functions.

cpuswitch.S needs a specific change: with "br x27" the CPU expects "bti j",
which is bad because the functions begin with "bti c"; switch to "br x16",
for the CPU to accept "bti c".

BTI helps defend against JOP/COP. Tested on Qemu.

Add support for Pointer Authentication (PAC).

We use the "pac-ret" option, to sign the return instruction pointer on
function entry, and authenticate it on function exit. This acts as a
mitigation against ROP.

The authentication uses a per-lwp (secret) I-A key stored in the 128bit
APIAKey register and part of the lwp context. During lwp creation, the
kernel generates a random key, and during context switches, it installs
the key of the target lwp on the CPU.

Userland cannot read the APIAKey register directly. However, it can sign
its pointers with it, because the register is architecturally shared
between userland and the kernel. Although part of the CPU design, it is
a bit of an undesired behavior, because it allows to forge valid kernel
pointers from userland. To avoid that, we don't share the key with
userland, and rather switch it in EL0<->EL1 transitions. This means that
when userland executes, a different key is loaded in APIAKey than the one
the kernel uses. For now the userland key is a fixed 128bit zero value.

The DDB stack unwinder is changed to strip the authentication code from
the pointers in lr.

Two problems are known:

* Currently the idlelwps' keys are not really secret. This is because
the RNG is not yet available when we spawn these lwps. Not overly
important, but would be nice to fix with UEFI RNG.
* The key switching in EL0<->EL1 transitions is not the most optimized
code on the planet. Instead of checking aarch64_pac_enabled, it would
be better to hot-patch the code at boot time, but there currently is
no hot-patch support on aarch64.

Tested on Qemu.

branches: 1.153.4;
Various updates and improvements to cpu start up on arm/aarch64

- start sharing more code around the AP startup messaging.
- call arm_cpu_topology_set early so that ci_core_id is available for
drivers, e.g. bcm2835_intr.c
- both arm and aarch64 now have
- a static cpu_info_store array
- the same arm_cpu_{hatched,mbox}

Sort a bit

Trailing whitespace

port the arm64 cpu topology setup for big.little to arm.

rename arm64 cpu_do_topology() to arm_cpu_do_topology() and
call it from both arm cpu_attach().

replace both aarch64_set_topology() inline code in arm
cpu_attach() with new arm_cpu_do_topology(), which is called
by the arm64 locore as well (possibly not needed, which would
allow it to become static.)

not yet tested on a real big.little armv7 system. tested
on rockpro64 and pinebook pro.

branches: 1.149.2;
Move all non-emulation-specific coredump code into the coredump module,
and remove all #ifdef COREDUMP conditional compilation. Now, the
coredump module is completely separated from the emulation modules, and
they can all be independently loaded and unloaded.

Welcome to 9.99.18 !

Merge the [pgoyette-compat] branch

Split armv7/armv8 tprof backend config logic from the fdt bus glue.

Add support for EFI runtime services on aarch64.

Provide generic start code that assumes the MMU is off and caches are
disabled as per the linux booting protocol for ARMv6 and ARMv7 boards.
u-boot image type should be changed to 'linux' for correct behaviour.

The new start code builds a minimal "bootstrap" L1PT with cached access
disabled and uses the same table for all processors. AP startup is
performed in less steps and more code is written in C.

The bootstrap tables and stack are placed into an (orphaned) section
"_init_memory" which is given to uvm when it is no longer used.

Various kernels have been converted to use this code and tested. Some
boards were provided by TNF. Thanks!

The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS
kernels. The GENERIC kernel will also work on RPI2 using u-boot.

Thanks to martin@ and aymeric@ for testing on parallella and nanosoc
respectively

Whitespace

Centralise defparam CONSADDR, CONSPEED, CONMODE and CONADDR into
opt_console.h and adjust.

Whitespace

remove reference to CPU_ARMV2, suggested by jmcneill@

Retire CPU_ARM2, CPU_ARM250 and CPU_ARM3, they are all leftovers of
acorn26.

ok jmcneill@ skrll@

branches: 1.139.2;
Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

branches: 1.138.2;
Remove port-acorn26

OK core@

G/C ARM32_NEW_VM_LAYOUT

Add CPU_CORTEXA35

defflag CPU_CORTEXA53

Add __HAVE_GENERIC_CPU_INITCLOCKS option. If set, don't export
cpu_initclocks from device drivers as common code (in this case FDT) will
provide its own copy.

Add support for ARM Power State Coordination Interface (PSCI).

branches: 1.132.2;
Recognize Cortex-A57 FPU, GIC, and Generic Timer.

Support pmap_pv_track and friends

According to the Cortex-A5 TRM, the CBAR register is not implemented and
always reads as 0x00000000. Add ARM_CBAR option to set this in kernel
config.

Add CPU_CORTEXA17

branches: 1.128.2;
Add option ARM_HAS_LPAE

branches: 1.127.2;
Support (untested) SHEEVA_L2_CACHE and SHEEVA_L2_CACHE_WT options.
Move prototypes out to <arm/cpufunc.h> to their own file.
Add sdcache routines to cpufunc_asm_sheeva.S
Add code sheeve_setup to init the sdcache and sdcache info.

branches: 1.126.2;
Make the ARM pmap use ASIDs, split TTBRs, and MP safe. This only happens for
ARMv6 or later CPUs. This means that on context switch that the TLBs and
caches no longer to cleaned/flushed. Also, eXecute Never (XN) protection has
been added so non-exec pages can not be run. Change the page size for ARMv6+
to be 8KB while allows a L1PT to be a normal page. This means that the L1PT
is not special. Use the XN support to only sync pages that are executed from.

defflag VERBOSE_INIT_ARM

cpu_cortex doesn't need the arm11 cpufuncs any more

CPU_ARMV[67] imply ARM32_DISABLE_ALIGNMENT_FAULTS
Make it explicit.

Nuke atomic.S since we have MI defined atomic ops

Rework to have CPU_PREARMV6, CPU_ARMV6, as well as CPU_ARMV7

branches: 1.120.2;
File VBAR option

Add a ARM_HAS_VBAR option which forces the use of the VBAR register. This
allows much code to deal with vector_page mappings to be eliminated. On a
BEAGLEBONE kernel, this saves 8KB of text and instructions that never have
to be executed. (The PJ4B has VBAR but doesn't implement the security
extensions it is part of so a method was needed to allow it use VBAR with
relying on the default test for the security extensions.)

Add CPU_ARMV7 and make CPU_PJ4B and CPU_CORTEX instantiate it.

Make PJ4B support code compilable.

Obtained from Marvell, Semihalf.

Add BUSDMA_COUNTERS option

Disable bzero_page_vfp and bcopy_page_vfp since it really isn't any faster
than memcpy.

Add code to use VFP(or Neon) instructions to zero or copy a page via
pmap_zero_page and pmap_copy_page. (Not hooked into vfp_init yet).
Requires FPU_VFP

ARMFPE hasn't compiled since NetBSD 4. Remove it.
Complete support for FPU_VFP.
fpregs now contains vfpreg.
XXX vfpreg only has space for 16 64-bit FP registers though VFPv3 and later
have 32 64-bit FP registers.

Add a PMAP_NEEDS_ALLOC_POOLPAGE / PMAP_ALLOC_POOLPAGE hook so systems can
allocate pool pages from a specific VM freelist.

add _ARM32_NEED_BUS_DMA_BOUNCE to opt_arm_bus_space.h (It's not really a
bus_space option but it's close enough).

branches: 1.110.2;
Add core locator to mainbus. Add support for attaching multiple CPUs

Rename ARM options PROCESS_ID_IS_CUR{CPU,LWP} to TPIDRPRW_IS_CUR{CPU,LWP}
since TPIDRPRW is the cp15 register name.
Initialize it early in start along with CI_ARM_CPUID.
Remove other initializations.
We alays have ci_curlwp.
Enable TIPRPRW_IS_CURCPU in std.beagle.
[tested on a beaglboard (cortex-a8)]

Rework VFP support to use PCU.
Add emulation of instruction which save/restore the VFP FPSCR.
Add a sysarch hook to VFP FPSCR manipulation.

[The emulation will be used by libc to store/fetch exception modes and
rounding mode on a per-thread basis.]

COMPAT_NETBSD32 support for ARM. Which is strange since ARM is already
32-bits. But the newer ARM ABI AAPCS changes the alignment of 64-bit
fields so structures need to copied in and out to deal with the alignment
change. This is a kludge but makes debugging of AAPCS support much easier.

Add support for the ARM1176JZS

Add intrbase locator to mainbus.

Begin support for Cortex A5, A7, A15 and expand A8 and A9 definitions.
Instead of testing all possible CPUids for a cortex, we know what range
a cortex will be so mask out the insignificant parts and do a single test.

branches: 1.103.2;
Require arm3_cache_flush for ARM2/ARM250.

branches: 1.102.2; 1.102.6;
Welcome to 5.99.53! Merge rmind-uvmplock branch:

- Reorganize locking in UVM and provide extra serialisation for pmap(9).
New lock order: [vmpage-owner-lock] -> pmap-lock.

- Simplify locking in some pmap(9) modules by removing P->V locking.

- Use lock object on vmobjlock (and thus vnode_t::v_interlock) to share
the locks amongst UVM objects where necessary (tmpfs, layerfs, unionfs).

- Rewrite and optimise x86 TLB shootdown code, make it simpler and cleaner.
Add TLBSTATS option for x86 to collect statistics about TLB shootdowns.

- Unify /dev/mem et al in MI code and provide required locking (removes
kernel-lock on some ports). Also, avoid cache-aliasing issues.

Thanks to Andrew Doran and Joerg Sonnenberger, as their initial patches
formed the core changes of this branch.

branches: 1.101.2;
Preliminary ARM11 MPCore support.

I have confirmed this commit doesn't affect existing evbarm kernels by
comparing binaries.

branches: 1.100.2;
Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.

Cleanup the armv7 changes. Add ARM_ARCH_7. Use CPU_CORTEX instead of
CPU_CORTEXA8 everywhere since there more types of Cortex than just the A8.
CPU_CORTEXA8 still exists but causes CPU_CORTEX to be defined.
Add CPU_CORTEXA9 as well. Use .arch armv7a to get us the isb/dsb
instructions.

Test booted to root device prompt on a Beagleboard.
All ARM kernels successfully test built.

PR port-arm/43299: Support added for igepv2/cortexa8/omap3530

Apply patch from PR, with build fixes. ok skrll, matt

branches: 1.97.2; 1.97.4;
Add write-through cache work-around for ARM11 as well as ARM9/ARM10. Analyzed
& tested on i.MX35 with help from Tsubai Masanari.